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Title: UART16550(Verilog) Download
 Description: Through various simulation module code is a standard module, can be used directly
 Downloaders recently: [More information of uploader 阿汤哥]
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UART16550兼容的串行通讯控制器(Verilog语言描述)\timescale.v
..............................................\uart_core.v
..............................................\uart_defines.v
..............................................\uart_in.v
..............................................\uart_out.v
..............................................\uart_recv.v
..............................................\uart_send.v
..............................................\uart_top.v
UART16550兼容的串行通讯控制器(Verilog语言描述)
    

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