Description: AD976 FPGA to realize the automatic sampling of the Verilog HDL program, the AD976 is the mode 2, i.e., to use the CS signal, already debugging succe
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File list (Check if you may need any files):
ad976_CS\ad976.dpf
........\ad976.qsf
........\assignment_defaults.qdf
........\db\ad976.db_info
........\..\ad976.lpc.txt
........\..\ad976.lpc.html
........\..\ad976.lpc.rdb
........\..\ad976.restore.qmsg
........\..\ad976.rtlv_sg_swap.cdb
........\..\ad976.rtlv.hdb
........\..\prev_cmp_ad976.restore.qmsg
........\..\ad976_cs.smp_dump.txt
........\..\ad976.fit.qmsg
........\..\ad976.pre_map.cdb
........\..\prev_cmp_ad976.map.qmsg
........\..\ad976.rtlv_sg.cdb
........\..\ad976.pre_map.hdb
........\..\ad976.cmp.rdb
........\..\ad976.map.cdb
........\..\ad976.cbx.xml
........\..\ad976.hif
........\..\ad976.asm.qmsg
........\..\ad976.sld_design_entry.sci
........\..\ad976.hier_info
........\..\ad976.map.logdb
........\..\ad976.tan.qmsg
........\..\prev_cmp_ad976_cs.qmsg
........\..\prev_cmp_ad976.fit.qmsg
........\..\prev_cmp_ad976.asm.qmsg
........\..\prev_cmp_ad976.tan.qmsg
........\..\ad976.map.qmsg
........\..\ad976.sgdiff.cdb
........\..\add_sub_1nh.tdf
........\..\ad976.sgdiff.hdb
........\..\ad976.eco.cdb
........\..\ad976.map.hdb
........\..\ad976.syn_hier_info
........\..\ad976.tmw_info
........\..\ad976.sld_design_entry_dsc.sci
........\..\ad976.tis_db_list.ddb
........\ad976.restore.rpt
........\ad976_cs.qpf
........\incremental_db\compiled_partitions\ad976.root_partition.map.kpt
........\..............\README
........\ad976.map.summary
........\ad976.pin
........\ad976.fit.summary
........\ad976.sof
........\ad976.pof
........\ad976.tan.summary
........\ad976.done
........\ad976.map.smsg
........\ad976.v.bak
........\ad976.v
........\ad976.fit.rpt
........\ad976.asm.rpt
........\ad976.tan.rpt
........\ad976.map.rpt
........\ad976.flow.rpt
........\ad976_cs.qws
........\incremental_db\compiled_partitions
........\db
........\incremental_db
ad976_CS
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