LDPC的Verilog程序源代码，包括仿真数据等\decode\add_m_seq.bsf
.......................................\......\add_m_seq.v
.......................................\......\add_m_seq.vwf
.......................................\......\clk_5div_1.bsf
.......................................\......\clk_5div_1.vhd
.......................................\......\cmp_state.ini
.......................................\......\cnt25.bsf
.......................................\......\cnt25.v
.......................................\......\cnt40.bsf
.......................................\......\cnt40.v
.......................................\......\cnt40.vwf
.......................................\......\cnu_5.v
.......................................\......\cnu_5.vwf
.......................................\......\cnu_6.v
.......................................\......\cnu_6.vwf
.......................................\......\databuffer.bsf
.......................................\......\databuffer.v
.......................................\......\databuffer.vwf
.......................................\......\datain_encode.bsf
.......................................\......\datain_encode.mif
.......................................\......\datain_encode.v
.......................................\......\datain_encode_bb.v
.......................................\......\.b\add_sub_0vh.tdf
.......................................\......\..\add_sub_54i.tdf
.......................................\......\..\add_sub_64i.tdf
.......................................\......\..\add_sub_6vh.tdf
.......................................\......\..\add_sub_74i.tdf
.......................................\......\..\add_sub_7vh.tdf
.......................................\......\..\add_sub_84i.tdf
.......................................\......\..\add_sub_gvd.tdf
.......................................\......\..\add_sub_knh.tdf
.......................................\......\..\add_sub_l2i.tdf
.......................................\......\..\add_sub_lnh.tdf
.......................................\......\..\add_sub_o2i.tdf
.......................................\......\..\add_sub_p2i.tdf
.......................................\......\..\add_sub_und.tdf
.......................................\......\..\add_sub_vuh.tdf
.......................................\......\..\altsyncram_3cv.tdf
.......................................\......\..\altsyncram_4ut.tdf
.......................................\......\..\altsyncram_5cv.tdf
.......................................\......\..\altsyncram_7mp.tdf
.......................................\......\..\altsyncram_8cv.tdf
.......................................\......\..\altsyncram_bm92.tdf
.......................................\......\..\altsyncram_c9r.tdf
.......................................\......\..\altsyncram_dfq.tdf
.......................................\......\..\altsyncram_hdv.tdf
.......................................\......\..\altsyncram_jm92.tdf
.......................................\......\..\altsyncram_lj92.tdf
.......................................\......\..\altsyncram_lm92.tdf
.......................................\......\..\altsyncram_m5u.tdf
.......................................\......\..\altsyncram_nm92.tdf
.......................................\......\..\altsyncram_pm92.tdf
.......................................\......\..\altsyncram_ptp.tdf
.......................................\......\..\altsyncram_r7q.tdf
.......................................\......\..\altsyncram_ugr.tdf
.......................................\......\..\cntr_0fc.tdf
.......................................\......\..\cntr_1a9.tdf
.......................................\......\..\cntr_218.tdf
.......................................\......\..\cntr_3a9.tdf
.......................................\......\..\cntr_4a9.tdf
.......................................\......\..\cntr_6a9.tdf
.......................................\......\..\cntr_718.tdf
.......................................\......\..\cntr_7v7.tdf
.......................................\