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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: UART Download
 Description: verilog to write the serial program, its function is completely the right, with the project file
 Downloaders recently: [More information of uploader panzdguof]
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File list (Check if you may need any files):
UART
....\Project
....\.......\Fusion_UART
....\.......\...........\component
....\.......\...........\constraint
....\.......\...........\..........\uart_test.pdc
....\.......\...........\coreconsole
....\.......\...........\designer
....\.......\...........\........\impl1
....\.......\...........\........\.....\designer.log
....\.......\...........\........\.....\designer_genhdl.log
....\.......\...........\........\.....\simulation
....\.......\...........\........\.....\uart_test.adb
....\.......\...........\........\.....\uart_test.dtf
....\.......\...........\........\.....\.............\verify.log
....\.......\...........\........\.....\uart_test.ide_des
....\.......\...........\........\.....\uart_test.pdb
....\.......\...........\........\.....\uart_test.pdb.depends
....\.......\...........\........\.....\uart_test.stp
....\.......\...........\........\.....\uart_test.tcl
....\.......\...........\........\.....\uart_test_ba.sdf
....\.......\...........\........\.....\uart_test_ba.v
....\.......\...........\hdl
....\.......\...........\...\hdlsynchk.tcl
....\.......\...........\...\rec.v
....\.......\...........\...\send.v
....\.......\...........\...\uart_test.v
....\.......\...........\phy_synthesis
....\.......\...........\simulation
....\.......\...........\..........\meminit.dat
....\.......\...........\..........\modelsim.ini
....\.......\...........\..........\modelsim.ini.sav
....\.......\...........\smartgen
....\.......\...........\........\smartgen.aws
....\.......\...........\stimulus
....\.......\...........\........\BtimErrors.log
....\.......\...........\........\files_to_build.txt
....\.......\...........\........\hdlsynchk.tcl
....\.......\...........\........\uart_test.dsk
....\.......\...........\........\uart_test.hpj
....\.......\...........\........\uart_test.v
....\.......\...........\........\uart_test_tbench.bk
....\.......\...........\........\uart_test_tbench.btim
....\.......\...........\........\uart_test_tbench.v
....\.......\...........\........\waveperl.log
....\.......\...........\synthesis
....\.......\...........\.........\.recordref
....\.......\...........\.........\backup
....\.......\...........\.........\rev_1
....\.......\...........\.........\.....\backup
....\.......\...........\.........\.....\coreip
....\.......\...........\.........\.....\run_options.txt
....\.......\...........\.........\.....\syntmp
....\.......\...........\.........\run_options.txt
....\.......\...........\.........\stdout.log
....\.......\...........\.........\synthesis_identify
....\.......\...........\.........\..................\syntmp
....\.......\...........\.........\..................\......\identify.msg
....\.......\...........\.........\..................\......\uart_test.msg
....\.......\...........\.........\..................\......\uart_test_flink.htm
....\.......\...........\.........\..................\uart_test.srs
....\.......\...........\.........\..................\uart_test.tlg
....\.......\...........\.........\syntmp
....\.......\...........\.........\......\sap.log
....\.......\...........\.........\......\uart_test.msg
....\.......\...........\.........\......\uart_test.plg
....\.......\...........\.........\......\uart_test_flink.htm
....\.......\...........\.........\......\uart_test_srr.htm
....\.......\...........\.........\......\uart_test_toc.htm
....\.......\...........\.........\traplog.tlg
....\.......\...........\.........\uart_test.areasrr
....\.......\...........\.........\uart_test.edn
....\.......\...........\.........\uart_test.fse
....\.......\...........\.........\uart_test.htm
....\.......\...........\.........\uart_test.map
....\.......\...........\.........\uart_test.sap
....\.......\...........\.........\uart_test.sdf
....\.......\...........\.........\uart_test.srd
....\.......\...........\.........\uart_test.srm
....\.......\...........\.........\uart_test.srr
....\.......\...........\.........\uart_test.srs
....\.......\...........\.........\uart_test.tlg
....\.......\...........\.........\uart_test_drc.rpt
....\.......\...........\.........\uart_tes

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