Description: Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian):
add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
of nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
sllv rd, rt, rs
sra rd, rt, shamt
blez rs, imm
j target
lwl rt, offset (base)
lwr rt, offset (base)
lw rt, imm (rs)
sw rt, imm (rs)
To Search:
File list (Check if you may need any files):
多周期流水线CPU\PipelineCPU\ALU.v
...............\...........\ALU.v.bak
...............\...........\BarrelShifter.v
...............\...........\BarrelShifter.v.bak
...............\...........\ControlHazard.v
...............\...........\ControlHazard.v.bak
...............\...........\ControlUnit.v
...............\...........\ControlUnit.v.bak
...............\...........\DataMemory.v
...............\...........\DataMemory.v.bak
...............\...........\db\altsyncram_02j1.tdf
...............\...........\..\altsyncram_4nq1.tdf
...............\...........\..\altsyncram_bb01.tdf
...............\...........\..\altsyncram_mjj1.tdf
...............\...........\..\altsyncram_mnv.tdf
...............\...........\..\altsyncram_ohn1.tdf
...............\...........\..\altsyncram_sqv.tdf
...............\...........\..\mux_3nc.tdf
...............\...........\..\mux_aqc.tdf
...............\...........\..\mux_d3d.tdf
...............\...........\..\mux_ioc.tdf
...............\...........\..\mux_umc.tdf
...............\...........\..\PipelineCPU.cbx.xml
...............\...........\..\PipelineCPU.cmp.rdb
...............\...........\..\PipelineCPU.cmp_merge.kpt
...............\...........\..\PipelineCPU.db_info
...............\...........\..\PipelineCPU.eco.cdb
...............\...........\..\PipelineCPU.eds_overflow
...............\...........\..\PipelineCPU.fnsim.cdb
...............\...........\..\PipelineCPU.fnsim.hdb
...............\...........\..\PipelineCPU.fnsim.qmsg
...............\...........\..\PipelineCPU.hier_info
...............\...........\..\PipelineCPU.hif
...............\...........\..\PipelineCPU.IFUnit0.rtl.mif
...............\...........\..\PipelineCPU.IUnit0.rtl.mif
...............\...........\..\PipelineCPU.lpc.html
...............\...........\..\PipelineCPU.lpc.rdb
...............\...........\..\PipelineCPU.lpc.txt
...............\...........\..\PipelineCPU.map.bpm
...............\...........\..\PipelineCPU.map.cdb
...............\...........\..\PipelineCPU.map.ecobp
...............\...........\..\PipelineCPU.map.hdb
...............\...........\..\PipelineCPU.map.kpt
...............\...........\..\PipelineCPU.map.logdb
...............\...........\..\PipelineCPU.map.qmsg
...............\...........\..\PipelineCPU.map_bb.cdb
...............\...........\..\PipelineCPU.map_bb.hdb
...............\...........\..\PipelineCPU.map_bb.logdb
...............\...........\..\PipelineCPU.PipelineCPU0.rtl.mif
...............\...........\..\PipelineCPU.pre_map.cdb
...............\...........\..\PipelineCPU.pre_map.hdb
...............\...........\..\PipelineCPU.ram0_DataMemory_5d7c1658.hdl.mif
...............\...........\..\PipelineCPU.ram0_Reg32_58fbfcc.hdl.mif
...............\...........\..\PipelineCPU.rtlv.hdb
...............\...........\..\PipelineCPU.rtlv_sg.cdb
...............\...........\..\PipelineCPU.rtlv_sg_swap.cdb
...............\...........\..\PipelineCPU.sgdiff.cdb
...............\...........\..\PipelineCPU.sgdiff.hdb
...............\...........\..\PipelineCPU.sim.cvwf
...............\...........\..\PipelineCPU.sim.hdb
...............\...........\..\PipelineCPU.sim.qmsg
...............\...........\..\PipelineCPU.sim.rdb
...............\...........\..\PipelineCPU.simfam
...............\...........\..\PipelineCPU.sld_design_entry.sci
...............\...........\..\PipelineCPU.sld_design_entry_dsc.sci
...............\...........\..\PipelineCPU.syn_hier_info
...............\...........\..\PipelineCPU.tis_db_list.ddb
...............\...........\..\PipelineCPU.tmw_info
...............\...........\..\prev_cmp_PipelineCPU.map.qmsg
...............\...........\..\prev_cmp_PipelineCPU.qmsg
...............\...........\..\prev_cmp_PipelineCPU.sim.qmsg
...............\...........\..\wed.wsf
...............\...........\Extender.v
...............\...........\Ex_Mem.v
...............\...........\Ex_Mem.v.bak
...............\...........\ForwardUnit.v
...............\...........\ForwardUnit.v.bak
...............\...........\ID_Ex.v
...............\...........\ID_Ex.v.bak
...............\...........\IF_ID.v
...............\...........\IF_ID.v.
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