Description: In the hardware circuit design, will produce a large number of Verilog HDL code, the code is automatically generated, the file name of no practical significance, code no comments, no relevant documentation, to read and understand the inconvenience
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comment.py
doc
files
.....\b01.v
.....\b02.v
.....\b03.v
.....\b04.v
.....\b05.v
.....\b06.v
.....\b07.v
.....\b08.v
.....\b09.v
.....\b10.v
.....\b11.v
.....\b12.v
.....\b13.v
.....\b14.v
.....\b15.v
.....\b17.v
.....\b18.v
.....\b20.v
.....\b21.v
.....\b22.v
.....\list.txt
gui.py
lib
...\comm.py
...\option.py
...\__init__.py
list.txt
logs
makefile
report.py
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