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《Verilog HDL数字控制系统设计实例》-冼进-源代码-4469\第4章.rar
....................................................\..9章\Slave_Control\Slave_Floor_Select\cmp_state.ini
....................................................\.....\.............\..................\Slave_Floor_Select.asm.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.bsf
....................................................\.....\.............\..................\Slave_Floor_Select.done
....................................................\.....\.............\..................\Slave_Floor_Select.fit.eqn
....................................................\.....\.............\..................\Slave_Floor_Select.fit.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.fit.summary
....................................................\.....\.............\..................\Slave_Floor_Select.flow.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.map.eqn
....................................................\.....\.............\..................\Slave_Floor_Select.map.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.map.summary
....................................................\.....\.............\..................\Slave_Floor_Select.pin
....................................................\.....\.............\..................\Slave_Floor_Select.pof
....................................................\.....\.............\..................\Slave_Floor_Select.qpf
....................................................\.....\.............\..................\Slave_Floor_Select.qsf
....................................................\.....\.............\..................\Slave_Floor_Select.qws
....................................................\.....\.............\..................\Slave_Floor_Select.sim.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.tan.rpt
....................................................\.....\.............\..................\Slave_Floor_Select.tan.summary
....................................................\.....\.............\..................\Slave_Floor_Select.v
....................................................\.....\.............\..................\Slave_Floor_Select.vwf
....................................................\.....\.............\..................\db\Slave_Floor_Select.asm.qmsg
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp.cdb
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp.ddb
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp.hdb
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp.rdb
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp.tdb
....................................................\.....\.............\..................\..\Slave_Floor_Select.cmp0.ddb
....................................................\.....\.............\..................\..\Slave_Floor_Select.db_info
....................................................\.....\.............\..................\..\Slave_Floor_Select.eco.cdb
....................................................\.....\.............\..................\..\Slave_Floor_Select.eds_overflow
....................................................\.....\.............\..................\..\Slave_Floor_Select.fit.qmsg
....................................................\.....\.............\..................\..\Slave_Floor_Select.hier_info
....................................................\.....\.............\..................\..\Sl

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