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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: shuzishizhong Download
 Description: This code is the FPGA' s digital clock code, the use of the verilog language.
 Downloaders recently: [More information of uploader 297505453]
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数字时钟\clock.asm.rpt
........\clock.cdf
........\clock.done
........\clock.dpf
........\clock.fit.eqn
........\clock.fit.rpt
........\clock.fit.smsg
........\clock.fit.summary
........\clock.flow.rpt
........\clock.map.eqn
........\clock.map.rpt
........\clock.map.summary
........\clock.pin
........\clock.pof
........\clock.qpf
........\clock.qsf
........\clock.qws
........\clock.tan.rpt
........\clock.tan.summary
........\clock.v
........\clock.v.bak
........\clock_assignment_defaults.qdf
........\cmp_state.ini
........\db\add_sub_bph.tdf
........\..\add_sub_onh.tdf
........\..\clock.db_info
........\..\clock.eco.cdb
........\..\clock.sld_design_entry.sci
........\..\clock_cmp.qrpt
........\db
数字时钟
    

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