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Title: flash02 Download
 Description: I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
 Downloaders recently: [More information of uploader AACCCBB]
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flash02\db\flash.asm.qmsg
.......\..\flash.asm.rdb
.......\..\flash.cbx.xml
.......\..\flash.cmp.bpm
.......\..\flash.cmp.cdb
.......\..\flash.cmp.ecobp
.......\..\flash.cmp.hdb
.......\..\flash.cmp.kpt
.......\..\flash.cmp.logdb
.......\..\flash.cmp.rdb
.......\..\flash.cmp.tdb
.......\..\flash.cmp0.ddb
.......\..\flash.cmp_merge.kpt
.......\..\flash.db_info
.......\..\flash.eco.cdb
.......\..\flash.eda.qmsg
.......\..\flash.fit.qmsg
.......\..\flash.hier_info
.......\..\flash.hif
.......\..\flash.lpc.html
.......\..\flash.lpc.rdb
.......\..\flash.lpc.txt
.......\..\flash.map.bpm
.......\..\flash.map.cdb
.......\..\flash.map.ecobp
.......\..\flash.map.hdb
.......\..\flash.map.kpt
.......\..\flash.map.logdb
.......\..\flash.map.qmsg
.......\..\flash.map_bb.cdb
.......\..\flash.map_bb.hdb
.......\..\flash.map_bb.logdb
.......\..\flash.merge.qmsg
.......\..\flash.pre_map.cdb
.......\..\flash.pre_map.hdb
.......\..\flash.rtlv.hdb
.......\..\flash.rtlv_sg.cdb
.......\..\flash.rtlv_sg_swap.cdb
.......\..\flash.sgdiff.cdb
.......\..\flash.sgdiff.hdb
.......\..\flash.sld_design_entry.sci
.......\..\flash.sld_design_entry_dsc.sci
.......\..\flash.smart_action.txt
.......\..\flash.smp_dump.txt
.......\..\flash.syn_hier_info
.......\..\flash.tan.qmsg
.......\..\flash.tis_db_list.ddb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_flash.asm.qmsg
.......\..\prev_cmp_flash.eda.qmsg
.......\..\prev_cmp_flash.fit.qmsg
.......\..\prev_cmp_flash.map.qmsg
.......\..\prev_cmp_flash.merge.qmsg
.......\..\prev_cmp_flash.qmsg
.......\..\prev_cmp_flash.tan.qmsg
.......\flash.asm.rpt
.......\flash.done
.......\flash.dpf
.......\flash.eda.rpt
.......\flash.fit.rpt
.......\flash.fit.smsg
.......\flash.fit.summary
.......\flash.flow.rpt
.......\flash.map.rpt
.......\flash.map.summary
.......\flash.merge.rpt
.......\flash.pin
.......\flash.pof
.......\flash.qpf
.......\flash.qsf
.......\flash.qws
.......\flash.sof
.......\flash.tan.rpt
.......\flash.tan.summary
.......\flash.v
.......\flash.v.bak
.......\flash_nativelink_simulation.rpt
.......\incremental_db\compiled_partitions\flash.root_partition.cmp.cdb
.......\..............\...................\flash.root_partition.cmp.dfp
.......\..............\...................\flash.root_partition.cmp.hdb
.......\..............\...................\flash.root_partition.cmp.kpt
.......\..............\...................\flash.root_partition.cmp.logdb
.......\..............\...................\flash.root_partition.cmp.rcfdb
.......\..............\...................\flash.root_partition.cmp.re.rcfdb
.......\..............\...................\flash.root_partition.map.cdb
.......\..............\...................\flash.root_partition.map.dpi
.......\..............\...................\flash.root_partition.map.hdb
.......\..............\...................\flash.root_partition.map.kpt
.......\..............\README
.......\simulation\modelsim\flash.sft
.......\..........\........\flash.vo
.......\..........\........\flash.vt
.......\..........\........\flash.vt.bak
.......\..........\........\flash_modelsim.xrf
.......\..........\........\flash_run_msim_rtl_verilog.do
.......\..........\........\flash_run_msim_rtl_verilog.do.bak
.......\..........\........\flash_run_msim_rtl_verilog.do.bak1
.......\..........\........\flash_run_msim_rtl_verilog.do.bak10
.......\..........\........\flash_run_msim_rtl_verilog.do.bak11
.......\..........\........\flash_run_msim_rtl_verilog.do.bak2
    

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