Description: Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
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File list (Check if you may need any files):
ADSample_FPGA\ADSample_Interface.asm.rpt
.............\ADSample_Interface.cdf
.............\ADSample_Interface.done
.............\ADSample_Interface.dpf
.............\ADSample_Interface.fit.rpt
.............\ADSample_Interface.fit.smsg
.............\ADSample_Interface.fit.summary
.............\ADSample_Interface.flow.rpt
.............\ADSample_Interface.jdi
.............\ADSample_Interface.map.rpt
.............\ADSample_Interface.map.summary
.............\ADSample_Interface.pin
.............\ADSample_Interface.pof
.............\ADSample_Interface.qpf
.............\ADSample_Interface.qsf
.............\ADSample_Interface.qws
.............\ADSample_Interface.sof
.............\ADSample_Interface.tan.rpt
.............\ADSample_Interface.tan.summary
.............\ADSample_Interface.tcl
.............\ADSample_Interface.v
.............\ADSample_Interface.v.bak
.............\ADSample_Interface_assignment_defaults.qdf
.............\DAC_TABLE.bsf
.............\DAC_TABLE.v
.............\DAC_TABLE_bb.v
.............\db\ADSample_Interface.db_info
.............\..\ADSample_Interface.eco.cdb
.............\..\ADSample_Interface.sld_design_entry.sci
.............\..\altsyncram_1ui2.tdf
.............\..\altsyncram_c4l1.tdf
.............\..\altsyncram_e7p3.tdf
.............\..\altsyncram_li91.tdf
.............\..\altsyncram_qgq1.tdf
.............\..\cmpr_3vh.tdf
.............\..\cntr_1sf.tdf
.............\..\cntr_2jg.tdf
.............\..\cntr_5if.tdf
.............\..\cntr_bbi.tdf
.............\..\cntr_cbi.tdf
.............\..\cntr_foh.tdf
.............\..\cntr_i4j.tdf
.............\..\cntr_uoe.tdf
.............\..\cntr_uti.tdf
.............\..\decode_aoi.tdf
.............\..\decode_rqf.tdf
.............\..\mux_boc.tdf
.............\..\prev_cmp_ADSample_Interface.asm.qmsg
.............\..\prev_cmp_ADSample_Interface.fit.qmsg
.............\..\prev_cmp_ADSample_Interface.map.qmsg
.............\..\prev_cmp_ADSample_Interface.qmsg
.............\..\prev_cmp_ADSample_Interface.tan.qmsg
.............\PLL10MHzx8.bsf
.............\PLL10MHzx8.ppf
.............\PLL10MHzx8_wave0.jpg
.............\PLL10MHzx8_waveforms.html
.............\PLL39MHzx3.bsf
.............\PLL39MHzx3.ppf
.............\PLL39MHzx3.v
.............\PLL39MHzx3_bb.v
.............\PLL39MHzx3_wave0.jpg
.............\PLL39MHzx3_waveforms.html
.............\sin.mif
.............\stp1.stp
.............\stp1_auto_signaltap_0.txt
.............\stp1_auto_signaltap_0.txt.bak
.............\db
ADSample_FPGA
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