Description: verilog digital interface for experimental procedures, including the matrix keyboard, buzzer, serial, i2c bus interface program instance.
- [NumClock] - based Altera FPGA series (Cyclone EP1C3T
- [Verilog] - Verilog routines very substantial inform
- [eeprom_i2c.tar] - I2C EEPROM verilog simulation model
- [I2C] - I2C/IIC Bus Driver, written in Verilog,
- [bfgd_fpga] - ARM9-implemented data collection and sto
File list (Check if you may need any files):
新建文件夹\i2c总线\.xhdl3.xref
..........\.......\cmp_state.ini
..........\.......\db\add_sub_5ph.tdf
..........\.......\..\add_sub_6ph.tdf
..........\.......\..\add_sub_dph.tdf
..........\.......\..\add_sub_rnh.tdf
..........\.......\..\i2c.asm.qmsg
..........\.......\..\i2c.cbx.xml
..........\.......\..\i2c.cmp.cdb
..........\.......\..\i2c.cmp.hdb
..........\.......\..\i2c.cmp.rdb
..........\.......\..\i2c.cmp.tdb
..........\.......\..\i2c.cmp0.ddb
..........\.......\..\i2c.db_info
..........\.......\..\i2c.eco.cdb
..........\.......\..\i2c.fit.qmsg
..........\.......\..\i2c.hier_info
..........\.......\..\i2c.hif
..........\.......\..\i2c.map.cdb
..........\.......\..\i2c.map.hdb
..........\.......\..\i2c.map.qmsg
..........\.......\..\i2c.pre_map.cdb
..........\.......\..\i2c.pre_map.hdb
..........\.......\..\i2c.psp
..........\.......\..\i2c.rtlv.hdb
..........\.......\..\i2c.rtlv_sg.cdb
..........\.......\..\i2c.rtlv_sg_swap.cdb
..........\.......\..\i2c.sgdiff.cdb
..........\.......\..\i2c.sgdiff.hdb
..........\.......\..\i2c.sld_design_entry.sci
..........\.......\..\i2c.sld_design_entry_dsc.sci
..........\.......\..\i2c.smp_dump.txt
..........\.......\..\i2c.syn_hier_info
..........\.......\..\i2c.tan.qmsg
..........\.......\..\i2c_cmp.qrpt
..........\.......\i2c.asm.rpt
..........\.......\i2c.cdf
..........\.......\i2c.done
..........\.......\i2c.fit.eqn
..........\.......\i2c.fit.rpt
..........\.......\i2c.fit.summary
..........\.......\i2c.flow.rpt
..........\.......\i2c.map.eqn
..........\.......\i2c.map.rpt
..........\.......\i2c.map.summary
..........\.......\i2c.pin
..........\.......\i2c.pof
..........\.......\i2c.qpf
..........\.......\i2c.qsf
..........\.......\i2c.qws
..........\.......\i2c.tan.rpt
..........\.......\i2c.tan.summary
..........\.......\i2c.v
..........\.......\i2c.v.bak
..........\.......\serv_req_info.txt
..........\series_to_parallel.qar
..........\USB\Chapter10 Sample\eth_clockgen.v
..........\...\................\eth_cop.v
..........\...\................\eth_crc.v
..........\...\................\eth_defines.v
..........\...\................\eth_fifo.v
..........\...\................\eth_host.v
..........\...\................\eth_maccontrol.v
..........\...\................\eth_macstatus.v
..........\...\................\eth_memory.v
..........\...\................\eth_miim.v
..........\...\................\eth_outputcontrol.v
..........\...\................\eth_phy.v
..........\...\................\eth_phy_defines.v
..........\...\................\eth_random.v
..........\...\................\eth_receivecontrol.v
..........\...\................\eth_register.v
..........\...\................\eth_registers.v
..........\...\................\eth_rxaddrcheck.v
..........\...\................\eth_rxcounters.v
..........\...\................\eth_rxethmac.v
..........\...\................\eth_rxstatem.v
..........\...\................\eth_shiftreg.v
..........\...\................\eth_spram_256x32.v
..........\...\................\eth_top.v
..........\...\................\eth_transmitcontrol.v
..........\...\................\eth_txcounters.v
..........\...\................\eth_txethmac.v
..........\...\................\eth_txstatem.v
..........\...\................\eth_wishbone.v
..........\...\................\tb_cop.v
..........\...\................\tb_ethernet.v
..........\...\................\tb_ethernet_with_cop.v
..........\...\................\tb_eth_defines.v
..........\...\................\tb_eth_top.v
..........\...\................\timescale.v
..........\...\................\wb_bus_mon.v
..........\...\................\wb_master32.v
..........\...\................\wb_master_behavioral.v
..........\...\................\wb_model_defines.v
..........\...\................\wb_slave_behavioral.v
..........\...\................\使用说明.txt
..........\...\.......4 Sample\I2C\automake.log
..........\...\...............\...\coregen.log
..........\...\...............\...\coregen.prj
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