E1 Analysis of frame synchronization algorithm, to

Title: E1

Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
94kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
lixun86

Description: Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics.

Downloaders recently: [More information of uploader lixun86]

To Search: E1

[pcm] - The board is opened with FRAMERS (E1), e
[Frame_Detection] - 802.11a frame detection source, includin
[frame_syn] - This is a frame synchronization data sea
[renesas_for_washingmachine] - Renesas MCU application code on the wash
[SDH_module] - SDH frame sync detection, and extract au

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E1.doc

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