PLL_50MHz_to_12MHz Verilog HDL language，EP2C8Q208 - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Embeded-SCM Develop

VHDL-FPGA-Verilog

Title: PLL_50MHz_to_12MHz

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
52kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
patton016

Description: Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency

Downloaders recently: [More information of uploader patton016]

To Search: ep2c8q p FPGA PLL CO

[verilogSDRAMcore] - I used to write Verilog HDL source of SD
[Ethernet_verilog_ip_core] - Ethernet (Ethernet) verilog ip core lang
[demo] - Bar lighting control project in the FPGA
[CPLD_Design_50] - 50 cases of practical CPLD design, very
[LCD12864IP] - 12864 of the IP, in the electronic studi
[usb.vhd] - USB functionality using FPGA simulation
[feisikaerbaogao] - The first three freescale intelligent ca

File list (Check if you may need any files):

PLL_12MHz\pll12MHz_waveforms.html
.........\pll12MHz_wave0.jpg
.........\pll12MHz.v
.........\pll12MHz.ppf
.........\pll12MHz.bsf
.........\pll12MHz_inst.v
.........\pll12MHz_bb.v
.........\pll12MHz.qip
PLL_12MHz

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.