Description: A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
- [vhdlfifo1] - fifo - source code for first in first ou
- [ex9] - I2C communication protocol of a verilog
- [conformPulse] - The program realization of two-phase hyb
- [FIFO] - FIFO control in the FPGA
File list (Check if you may need any files):
vspi\vspi.v
....\vspi.vhd
vspi
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