vga_ip_v1_00_a\data\vga_ip_v2_1_0.mpd
..............\....\vga_ip_v2_1_0.pao
..............\....\_vga_ip_xst.prj
..............\...._old\vga_ip_v2_1_0.mpd
..............\........\vga_ip_v2_1_0.pao
..............\.evl\create.cip
..............\....\ipwiz.log
..............\....\ipwiz.opt
..............\....\projnav\vga_ip.gise
..............\....\.......\vga_ip.ise
..............\....\.......\vga_ip.tcl
..............\....\.......\vga_ip.xise
..............\....\README.txt
..............\....\synthesis\vga_ip_xst.prj
..............\....\.........\vga_ip_xst.scr
..............\hdl\verilog\user_logic.v
..............\...\.hdl\vga_ip.vhd
..............\devl\projnav\vga_ip_xdb\tmp
..............\....\.......\vga_ip_xdb
..............\....\.......\_xmsgs
..............\....\projnav
..............\....\synthesis
..............\hdl\verilog
..............\...\vhdl
..............\data
..............\data_old
..............\devl
..............\hdl
vga_ip_v1_00_a