FIFO Fpga-based asynchronous design and implementa - CodeBus

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VHDL-FPGA-Verilog

Title: FIFO

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
3kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
ly80ning

Description: Fpga-based asynchronous FIFO design and implementation of source code

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File list (Check if you may need any files):

异步FIFO设计\async_cmp.v
............\async_fifo.v
............\dp_ram.v
............\rptr_empty.v
............\wptr_full.v
异步FIFO设计

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