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Title: UART Download
 Description: Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
 To Search: uart verilog
  • [usart_verilog] - Uart verilog code
  • [uart] - uart vhdl quartus
  • [UART] - UART
  • [UART] - I have written of the FPGA asynchronous
  • [uartverilog] - Verilog Uart classic example, training f
  • [SDRAMcontroller] - a paper about the information and descri
  • [I2C] - Language: verilog Function: I2C written
  • [RS232(verilog)] - RS232 serial communication program, incl
  • [ddsfinal1] - verilog language dds code,modelsim debug
  • [uart] - verilog uart prepared to send and receiv
File list (Check if you may need any files):
UART\ClkUnit.v
....\clk_1_wave0.jpg
....\clk_pll.v
....\clk_pll_bb.v
....\clk_pll_wave0.jpg
....\control_UART.v
....\miniUART.v
....\Rx_Unit.v
....\test_uart.v
....\Tx_Unit.v
....\UART.v
UART
    

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