Description: In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
- [cordic_3] - Pipelined structure cordic, can output s
- [CORDIC_ip] - cordic IP coreFeatures Each file is stan
- [cordic_4] - VHDL coding cordic
- [cordic-verilog] - Written using Verilog cordic phase ident
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10_cordic算法\10_cordic算法.rar
10_cordic算法
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