Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: DigitalClock Download
 Description: The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
 Downloaders recently: [More information of uploader nju.fushibin]
 To Search:
File list (Check if you may need any files):
DigitalClock\bin47seg.bsf
............\bin47seg.v
............\clk4hz.bsf
............\clk4hz.v
............\clk5mhz.bsf
............\clk5mhz.v
............\cnt8b.bsf
............\cnt8b.v
............\combine.bsf
............\combine.v
............\control.bsf
............\control.v
............\counter100.bsf
............\counter100.v
............\counter100.vwf
............\counter24.bsf
............\counter24.v
............\counter4.bsf
............\counter4.v
............\counter60.bsf
............\counter60.v
............\counter60.vwf
............\data_1to2.bsf
............\data_1to2.v
............\data_1to4.bsf
............\data_1to4.v
............\data_sec.bsf
............\data_sec.v
............\.b\add_sub_4rh.tdf
............\..\add_sub_msh.tdf
............\..\altsyncram_6sl.tdf
............\..\cntr_9gd.tdf
............\..\DigitalClock.asm.qmsg
............\..\DigitalClock.cbx.xml
............\..\DigitalClock.cmp.cdb
............\..\DigitalClock.cmp.hdb
............\..\DigitalClock.cmp.qrpt
............\..\DigitalClock.cmp.rdb
............\..\DigitalClock.cmp.tdb
............\..\DigitalClock.cmp0.ddb
............\..\DigitalClock.dbp
............\..\DigitalClock.db_info
............\..\DigitalClock.eco.cdb
............\..\DigitalClock.eds_overflow
............\..\DigitalClock.fit.qmsg
............\..\DigitalClock.fnsim.hdb
............\..\DigitalClock.fnsim.qmsg
............\..\DigitalClock.hier_info
............\..\DigitalClock.hif
............\..\DigitalClock.map.cdb
............\..\DigitalClock.map.hdb
............\..\DigitalClock.map.qmsg
............\..\DigitalClock.pre_map.cdb
............\..\DigitalClock.pre_map.hdb
............\..\DigitalClock.psp
............\..\DigitalClock.rtlv.hdb
............\..\DigitalClock.rtlv_sg.cdb
............\..\DigitalClock.rtlv_sg_swap.cdb
............\..\DigitalClock.sgdiff.cdb
............\..\DigitalClock.sgdiff.hdb
............\..\DigitalClock.signalprobe.cdb
............\..\DigitalClock.sim.hdb
............\..\DigitalClock.sim.qmsg
............\..\DigitalClock.sim.qrpt
............\..\DigitalClock.sim.rdb
............\..\DigitalClock.sim.vwf
............\..\DigitalClock.sld_design_entry.sci
............\..\DigitalClock.sld_design_entry_dsc.sci
............\..\DigitalClock.syn_hier_info
............\..\DigitalClock.tan.qmsg
............\..\DigitalClock0.rtl.mif
............\..\mux_4fc.tdf
............\..\mux_6fc.tdf
............\..\mux_9fc.tdf
............\..\mux_sgc.tdf
............\DigitalClock.asm.rpt
............\DigitalClock.bdf
............\DigitalClock.cdf
............\DigitalClock.done
............\DigitalClock.dpf
............\DigitalClock.fit.eqn
............\DigitalClock.fit.rpt
............\DigitalClock.fit.summary
............\DigitalClock.fld
............\DigitalClock.flow.rpt
............\DigitalClock.map.eqn
............\DigitalClock.map.rpt
............\DigitalClock.map.summary
............\DigitalClock.pin
............\DigitalClock.pof
............\DigitalClock.qpf
............\DigitalClock.qsf
............\DigitalClock.qws
............\DigitalClock.sim.rpt
............\DigitalClock.sof
............\DigitalClock.tan.rpt
............\DigitalClock.tan.summary
............\jiaoshi.v
............\lpm_mux0.bsf
............\lpm_mux0.v
    

CodeBus www.codebus.net