Floating-Point-Adder Floating point adder design I

Title: Floating-Point-Adder

Category:
VHDL-FPGA-Verilog
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File Size:
151kb
Update:
2012-11-26
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Uploaded by:
afengai2009

Description: Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.

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To Search: double precision floating point adder pipeline double precision floating point addition

[vhdldesign] - The VHDL algorithm of floating point add
[loongson] - Godson 2E processor user manual CAS Inst
[testbench] - The preparation of the very issue of Tes
[waterline_adder] - This is a Verilog prepared with four pip
[fir_512_378_mux] - 512-order high-speed FIR shaping filter,
[floatmul] - 32 floating-point implementation using v
[post_norm_mul] - 32-bit floating point pipeline multiplie
[floatadd] - floating_piont addition
[VHDLsample] - This file contains a selection of VHDL s
[SeniorFPGADesign] - Department of Electronic Engineering of

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浮点数加法器IP核的vhd设计.pdf

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