Description: this is verilog program for sysnchronous FIFO ,this document contains some error using before correct and then use,
- [Memory] - Example of a FIFO code in verilog langua
- [source_code] - verilog code fifo memory usb
File list (Check if you may need any files):
fifo\automake.log
....\coregen.log
....\coregen.prj
....\fifo.dhp
....\fifo.npl
....\FIFO1.ANT
....\fifo1.tbw
....\FIFO1.TFW
....\fifo2.v
....\fifo21.v
....\fifosyn2.v
....\fifosysn1.v
....\prjname.lso
....\sync_fifo.cmd_log
....\sync_fifo.lso
....\sync_fifo.ngr
....\sync_fifo.prj
....\sync_fifo.stx
....\sync_fifo.syr
....\sync_fifo_vhdl.prj
....\synfifo.v
....\syn_fifo.cmd_log
....\syn_fifo.lso
....\syn_fifo.prj
....\syn_fifo.syr
....\syn_fifo_vhdl.prj
....\xst
....\...\work
....\...\....\hdllib.ref
....\...\....\vlg20
....\...\....\.....\sync_fifo.bin
....\...\....\vlg29
....\...\....\.....\syn_fifo.bin
....\...\....\vlg31
....\...\....\.....\ram_dp_ar.bin
....\__projnav
....\.........\coregen.rsp
....\.........\fifo.gfl
....\.........\fifo_flowplus.gfl
....\.........\hb_cmds
....\.........\runXst_tcl.rsp
....\.........\sync_fifo.xst
....\.........\syn_fifo.xst
....\.........\xst_sprjTOstx_tcl.rsp
....\__projnav.log
fifo
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