spi4_to_4spi3\hdl
.............\...\verilog
.............\...\.......\bridge_top.v
.............\...\.......\pl4_v8_1_pl4_snk_top.v
.............\...\.......\pl4_v8_1_pl4_src_top.v
.............\...\.......\spi3_link_v4_1_spi3_link_rx.v
.............\...\.......\spi3_link_v4_1_spi3_link_tx.v
.............\...\.......\spi3_to_spi4_arbiter.v
.............\...\.......\spi3_to_spi4_burst_storage.v
.............\...\.......\spi3_to_spi4_core.v
.............\...\.......\spi3_to_spi4_read.v
.............\...\.......\spi3_to_spi4_top.v
.............\...\.......\spi3_to_spi4_write.v
.............\...\.......\spi4_to_spi3_burst_storage.v
.............\...\.......\spi4_to_spi3_core.v
.............\...\.......\spi4_to_spi3_flow_control.v
.............\...\.......\spi4_to_spi3_read.v
.............\...\.......\spi4_to_spi3_top.v
.............\...\.......\spi4_to_spi3_write.v
.............\...\.......\spi_clk_startup.v
.............\...\.......\spi_pkg.v
.............\...\vhdl
.............\...\....\bridge_top.vhd
.............\...\....\pl4_snk_top0_wrapper.vhd
.............\...\....\spi3_to_spi4_arbiter.vhd
.............\...\....\spi3_to_spi4_burst_storage.vhd
.............\...\....\spi3_to_spi4_core.vhd
.............\...\....\spi3_to_spi4_read.vhd
.............\...\....\spi3_to_spi4_top.vhd
.............\...\....\spi3_to_spi4_write.vhd
.............\...\....\spi4_to_spi3_burst_storage.vhd
.............\...\....\spi4_to_spi3_core.vhd
.............\...\....\spi4_to_spi3_flow_control.vhd
.............\...\....\spi4_to_spi3_read.vhd
.............\...\....\spi4_to_spi3_top.vhd
.............\...\....\spi4_to_spi3_write.vhd
.............\...\....\spi_clk_startup.vhd
.............\...\....\spi_pkg.vhd
.............\implement
.............\.........\bridge_top.ucf
.............\.........\bridge_top.ut
.............\.........\ngc
.............\.........\...\verilog
.............\.........\...\.......\generic_sfifo_512x72.ngo
.............\.........\...\.......\generic_sfifo_512x72_fifo_generator_v3_1_xst_1.ngc
.............\.........\...\vhdl
.............\.........\...\....\generic_sfifo_512x72.ngo
.............\.........\run_verilog.bat
.............\.........\run_vhd.bat
.............\readme.txt
.............\simulation
.............\..........\verilog
.............\..........\.......\generic_sfifo_512x72.v
.............\..........\.......\glbl.v
.............\..........\.......\master_clocks.v
.............\..........\.......\simulate.do
.............\..........\.......\spi3_emulator_phy.v
.............\..........\.......\spi3_phy_para.v
.............\..........\.......\spi4_to_4spi3_tb.v
.............\..........\.......\vlog.do
.............\..........\.......\vsim.do
.............\..........\.......\wave.do
.............\..........\vhdl
.............\..........\....\generic_sfifo_512x72.vhd
.............\..........\....\master_clocks.vhd
.............\..........\....\simulate.do
.............\..........\....\spi3_emulator_phy.vhd
.............\..........\....\spi4_to_4spi3_tb.vhd
.............\..........\....\vcom.do
.............\..........\....\vsim.do
.............\..........\....\wave.do
.............\synth
.............\.....\verilog
.............\.....\.......\bridge_top.lso
.............\.....\.......\bridge_top.prj
.............\.....\.......\bridge_top.prj.bak
.............\.....\.......\bridge_top.xst
.............\.....\.......\bridge_top.xst.bak
.............\.....\.......\bridge_top_vhdl.prj
.............\.....\.......\run_xst.bat
.............\.....\.......\xst
.............\.....\.......\...\dump.xst
.............\.....\.......\...\........\bridge_top.prj
.............\.....\.......\...\........\..............\ngx
.............\.....\.......\...\........\..............\...\notopt
.............\.....\.......\...\........\..............\...\opt
.............\.....\.......\...\projnav.tmp
.............\.....\.......\...\work
.............\.....\.......\...\....\hdllib.ref
.............\.....\.......\...\....\vlg0F
.............\.....\.......\...\....\.....\bridge__top.bin
.............\.....\.......\...\....\vlg1C
...........