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Title: Core8051 Download
 Description: 8051 ipcore VHDL CODE
 Downloaders recently: [More information of uploader fpgastation]
 To Search: core8051
File list (Check if you may need any files):
Core8051
........\component
........\constraint
........\coreconsole
........\...........\common
........\...........\......\A7S
........\...........\......\...\bfm
........\...........\......\...\...\compiler
........\...........\......\...\...\rtl
........\...........\......\...\...\...\verilog
........\...........\......\...\common
........\...........\......\...\......\timingshell
........\...........\......\...\......\...........\verilog
........\...........\......\...\M7AFS600-2
........\...........\......\...\..........\nodebug
........\...........\......\...\..........\.......\constraints
........\...........\......\...\..........\.......\layout
........\...........\......\...\..........\.......\timingshell
........\...........\......\...\..........\.......\...........\verilog
........\...........\......\COREUART
........\...........\......\........\mti
........\...........\......\........\...\lib_vlog_eval
........\...........\......\........\...\.............\COREUART_LIB
........\...........\......\........\...\.............\............\@c@o@r@e@u@a@r@t
........\...........\......\........\...\.............\............\@c@u@a@r@t@o1
........\...........\......\........\...\.............\............\@c@u@a@r@tl0
........\...........\......\........\...\.............\............\@c@u@a@r@tl1@i
........\...........\......\........\...\.............\............\@clock_gen
........\...........\......\........\...\.............\............\@rx_async
........\...........\......\........\...\.............\............\@tx_async
........\...........\......\........\...\.............\............\testbnch
........\...........\......\........\...\scripts
........\...........\......\........\rtl
........\...........\......\........\...\vlog
........\...........\......\........\...\....\core_obfuscated
........\...........\......\........\...\....\test
........\...........\......\........\...\....\....\verif
........\...........\r
........\...........\.\BusDefinitions
........\...........\.\r_A7S
........\...........\ws
........\...........\..\BusDefinitions
........\...........\..\ws_COREUART
........\designer
........\........\impl1
........\........\.....\simulation
........\........\.....\USER_CORE8051.dtf
........\........\.....\USER_CORE8051_fp
........\........\.....\................\projectData
........\hdl
........\phy_synthesis
........\simulation
........\smartgen
........\........\pll18m
........\........\pll33m
........\........\RAM2048X8
........\........\RAM256X8
........\........\RAM2KX8
........\stimulus
........\synthesis
........\.........\backup
........\.........\syntmp
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\wir
........\Core8051.prj
........\coreconsole\common\A7S\A7S.cxf
........\...........\......\...\bfm\compiler\bfmCompile.tcl
........\...........\......\...\...\rtl\verilog\a7sBFM.v
........\...........\......\...\...\...\.......\a7sBFM_TS.v
........\...........\......\...\...\subsystem.bfm
........\...........\......\...\common\timingshell\verilog\arm_other.v
........\...........\......\...\M7AFS600-2\nodebug\constraints\arm_palace.pdc
........\...........\......\...\..........\.......\layout\arm_designer.cdb
........\...........\......\...\..........\.......\timingshell\arm_palace.lib
........\...........\......\...\..........\.......\...........\verilog\arm_precision.v
........\...........\......\...\..........\.......\...........\.......\arm_synplify.v
........\...........\......\COREUART\coreparameters.v
........\...........\......\........\COREUART.cxf
........\...........\......\........\mti\lib_vlog_eval\COREUART_LIB\@c@o@r@e@u@a@r@t\verilog.psm
........\...........\......\........\...\.............\............\................\_primary.dat
........\...........\......\........\...\.............\............\................\_primary.vhd
........\...........\......\........\...\.............\............\...u@a@r@t@o1\verilog.psm
........\...........\......\........\...\.............\............\.............\_primary.dat

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