Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: hdb3 Download
 Description: vhdl language HDB3 encoder, applied four shift register, the output of 5-bit delay.
 Downloaders recently: [More information of uploader wang-xuchen]
 To Search: hdb3 hdb3 vhdl
  • [hdb3] - vhdl
  • [HDB3_coder] - Achieved the 64K low-speed NRZ code 2.04
  • [hdb3_decode] - hdb3 code encoding and decoding code, in
File list (Check if you may need any files):
hdb3\cmp_state.ini
....\db\add_sub_ith.tdf
....\..\hdb3.cbx.xml
....\..\hdb3.cmp.rdb
....\..\hdb3.db_info
....\..\hdb3.eco.cdb
....\..\hdb3.eds_overflow
....\..\hdb3.fnsim.cdb
....\..\hdb3.fnsim.hdb
....\..\hdb3.hier_info
....\..\hdb3.hif
....\..\hdb3.map.cdb
....\..\hdb3.map.hdb
....\..\hdb3.map.logdb
....\..\hdb3.map.qmsg
....\..\hdb3.pre_map.cdb
....\..\hdb3.pre_map.hdb
....\..\hdb3.psp
....\..\hdb3.rtlv.hdb
....\..\hdb3.rtlv_sg.cdb
....\..\hdb3.rtlv_sg_swap.cdb
....\..\hdb3.sgdiff.cdb
....\..\hdb3.sgdiff.hdb
....\..\hdb3.sim.hdb
....\..\hdb3.sim.qmsg
....\..\hdb3.sim.rdb
....\..\hdb3.sim.vwf
....\..\hdb3.sld_design_entry.sci
....\..\hdb3.sld_design_entry_dsc.sci
....\..\hdb3.syn_hier_info
....\..\hdb3.tan.qmsg
....\..\hdb3_cmp.qrpt
....\..\hdb3_sim.qrpt
....\..\mux_gdc.tdf
....\hdb3.done
....\hdb3.flow.rpt
....\hdb3.map.eqn
....\hdb3.map.rpt
....\hdb3.map.summary
....\hdb3.qpf
....\hdb3.qsf
....\hdb3.qws
....\hdb3.sim.rpt
....\hdb3.vhd
....\hdb3.vwf
....\db
hdb3
    

CodeBus www.codebus.net