Description: digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch.
platform: quartusII 5.1
comment: there s a place to change if you want the clock to tick at an actual speed. Find it ,change it and have fun with it!
To Search:
File list (Check if you may need any files):
e7v4\5bitbin2dec.v
....\6bitbin2dec.v
....\base.bdf
....\base.bsf
....\bin2dec.bsf
....\bin2dec.v
....\bin2seg.bsf
....\bin2seg.v
....\bitsel.bsf
....\bitsel.v
....\BitSelect.bdf
....\BitSelect.bsf
....\blink.bsf
....\blink.v
....\Clock.bdf
....\Clock.bsf
....\cnt_en.bsf
....\cnt_en.v
....\db\abs_divider_g7f.tdf
....\..\abs_divider_h7f.tdf
....\..\abs_divider_i7f.tdf
....\..\add_sub_f6b.tdf
....\..\add_sub_g6b.tdf
....\..\add_sub_h6b.tdf
....\..\add_sub_i6b.tdf
....\..\add_sub_ke8.tdf
....\..\add_sub_le8.tdf
....\..\add_sub_me8.tdf
....\..\add_sub_ne8.tdf
....\..\add_sub_oe8.tdf
....\..\add_sub_pe8.tdf
....\..\alt_u_div_fld.tdf
....\..\alt_u_div_hld.tdf
....\..\alt_u_div_jld.tdf
....\..\cntr_28g.tdf
....\..\cntr_38g.tdf
....\..\cntr_6ag.tdf
....\..\cntr_79f.tdf
....\..\cntr_89f.tdf
....\..\cntr_99f.tdf
....\..\cntr_9ff.tdf
....\..\cntr_ddg.tdf
....\..\cntr_dpf.tdf
....\..\cntr_f7g.tdf
....\..\cntr_fsg.tdf
....\..\cntr_kaf.tdf
....\..\cntr_opf.tdf
....\..\cntr_paf.tdf
....\..\cntr_pdf.tdf
....\..\cntr_pgf.tdf
....\..\cntr_psg.tdf
....\..\cntr_pug.tdf
....\..\cntr_qsg.tdf
....\..\cntr_tqf.tdf
....\..\cntr_ttf.tdf
....\..\cntr_tvg.tdf
....\..\decode_m0b.tdf
....\..\digclk.asm.qmsg
....\..\digclk.cbx.xml
....\..\digclk.cmp.cdb
....\..\digclk.cmp.hdb
....\..\digclk.cmp.qrpt
....\..\digclk.cmp.rdb
....\..\digclk.cmp.tdb
....\..\digclk.cmp0.ddb
....\..\digclk.dbp
....\..\digclk.db_info
....\..\digclk.eco.cdb
....\..\digclk.eds_overflow
....\..\digclk.fit.qmsg
....\..\digclk.fnsim.hdb
....\..\digclk.fnsim.qmsg
....\..\digclk.hier_info
....\..\digclk.hif
....\..\digclk.map.cdb
....\..\digclk.map.hdb
....\..\digclk.map.qmsg
....\..\digclk.pre_map.cdb
....\..\digclk.pre_map.hdb
....\..\digclk.psp
....\..\digclk.rtlv.hdb
....\..\digclk.rtlv_sg.cdb
....\..\digclk.rtlv_sg_swap.cdb
....\..\digclk.sgdiff.cdb
....\..\digclk.sgdiff.hdb
....\..\digclk.signalprobe.cdb
....\..\digclk.sim.hdb
....\..\digclk.sim.qmsg
....\..\digclk.sim.qrpt
....\..\digclk.sim.rdb
....\..\digclk.sim.vwf
....\..\digclk.sld_design_entry.sci
....\..\digclk.sld_design_entry_dsc.sci
....\..\digclk.syn_hier_info
....\..\digclk.tan.qmsg
....\..\lpm_abs_g45.tdf
....\..\lpm_abs_h45.tdf
....\..\lpm_abs_i45.tdf
....\..\lpm_abs_j45.tdf
....\..\lpm_divide_b3i.tdf
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