spi_core_open SPI master design

Title: spi_core_open

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2012-11-26
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wangnaidi

Description: SPI master design

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To Search: SPI VHDL SPI master vhdl

[SPI_Code(Verilog)] - SPI bus under the Verilog hardware descr
[spi_boot-rel_3_2_rev_C.tar] - spi bootloader detailed information, whi
[SPI_collect] - Related to the VHDL SPI realize. Includi
[spi] - A relatively good spi interface realize
[SPI] - VHDL language used to write SPI, contain
[xapp348] - spi-source is the verliog, reference may
[spiflashcontroller_latest.tar] - This VHDL module implements a state cont
[spi_slave] - Simple SPI slave with MOSI MISO SCLK SS
[conjoined] - SPI protocol: Serial Periphral Interface

File list (Check if you may need any files):

spi_op_core
...........\spi_op_core
...........\...........\spi.pdf
...........\...........\spi_clgen.v
...........\...........\spi_clgen.v.bak
...........\...........\spi_defines.v
...........\...........\spi_shift.v
...........\...........\spi_shift.v.bak
...........\...........\spi_top.v
...........\...........\spi_top.v.bak
...........\...........\tb
...........\...........\..\spi_slave_model.v
...........\...........\..\spi_slave_model.v.bak
...........\...........\..\tb_spi_top.v
...........\...........\..\tb_spi_top.v.bak
...........\...........\..\wb_master_model.v
...........\...........\..\wb_master_model.v.bak
...........\...........\timescale.v
...........\...........\transcript

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