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Title: CPU Download
 Description: Xilinx Modelsim produced the design of the processor, and add an external interface.
 To Search: VHDL Modelsim
  • [I2Cdesign] - I2C bus Verilog source code description,
  • [ADC_INTERFACE] - it is a verilog code written for MAX1886
File list (Check if you may need any files):
mycpu
.....\.untf
.....\alu.cmd_log
.....\alu.lso
.....\alu.ngc
.....\alu.ngr
.....\alu.prj
.....\alu.stx
.....\alu.syr
.....\alu.vhdl
.....\automake.log
.....\bitgen.ut
.....\coregen.log
.....\coregen.prj
.....\cpu管脚.txt
.....\getorder.cmd_log
.....\getorder.lso
.....\getorder.ngc
.....\getorder.ngr
.....\getorder.prj
.....\getorder.stx
.....\getorder.syr
.....\getorder.vhdl
.....\memctrl.cmd_log
.....\memctrl.lso
.....\memctrl.ngc
.....\memctrl.ngr
.....\memctrl.prj
.....\memctrl.stx
.....\memctrl.syr
.....\memctrl.vhdl
.....\MYCLK.txt
.....\mycpu.dhp
.....\mycpu.npl
.....\pepExtractor.prj
.....\results.txt
.....\Talu.ANT
.....\Talu.fdo
.....\Talu.tbw
.....\Talu.udo
.....\Talu.vhw
.....\Tgetorder.ANT
.....\Tgetorder.fdo
.....\Tgetorder.tbw
.....\Tgetorder.udo
.....\Tgetorder.vhw
.....\timeclk.cmd_log
.....\timeclk.lso
.....\timeclk.ngc
.....\timeclk.ngr
.....\timeclk.prj
.....\timeclk.stx
.....\timeclk.syr
.....\timeclk.vhdl
.....\Tmemctrl.ANT
.....\Tmemctrl.tbw
.....\Tmemctrl.vhw
.....\totoal.bgn
.....\totoal.bit
.....\totoal.bld
.....\totoal.cmd_log
.....\totoal.drc
.....\totoal.lso
.....\totoal.mrp
.....\totoal.nc1
.....\totoal.ncd
.....\totoal.ngc
.....\totoal.ngd
.....\totoal.ngm
.....\totoal.ngr
.....\totoal.pad
.....\totoal.pad_txt
.....\totoal.par
.....\totoal.pcf
.....\totoal.placed_ncd_tracker
.....\totoal.prj
.....\totoal.routed_ncd_tracker
.....\totoal.stx
.....\totoal.syr
.....\totoal.twr
.....\totoal.twx
.....\totoal.ucf
.....\totoal.ucf.untf
.....\totoal.ut
.....\totoal.vhdl
.....\totoal.xpi
.....\totoal_last_par.ncd
.....\totoal_map.ncd
.....\totoal_map.ngm
.....\totoal_pad.csv
.....\totoal_pad.txt
.....\transcript
.....\Ttimeclk.ANT
.....\Ttimeclk.fdo
.....\Ttimeclk.tbw
.....\Ttimeclk.udo
.....\Ttimeclk.vhw
.....\Ttotoal.ANT
.....\Ttotoal.fdo
.....\Ttotoal.tbw
    

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