watchver watchdog with verilog

Title: watchver

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Category:
software engineering
Tags:
[VHDL] [源码]
File Size:
138kb
Update:
2012-11-26
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Uploaded by:
yuhding_chang

Description: watchdog with verilog

Downloaders recently: [More information of uploader yuhding_chang]

To Search: watchdog verilog Verilog Watchdog VHDL watchdog

[modulewdt] - verilog language with the watchdog modul
[watch_dog] - Watchdog of the Verilog source code, par
[watch_dog_rtl_source] - Watchdog timer verilog RTL code
[watchdog] - Watchdog verilog source.
[Watchdog] - Based on the VHDL language, and practica

File list (Check if you may need any files):

watchver
........\cnt60.v
........\dcm1.v
........\dcm1.xaw
........\dcm1_arwz.ucf
........\decode.v
........\hex2led.v
........\readme
........\smallcntr.v
........\statmach.v
........\stopwatch.v
........\stopwatch.vcd
........\stopwatch_tb.tf
........\stopwatch_tb.v
........\stopwatch_tb_timing.tf
........\tenths.edn
........\tenths.v
........\tenths.veo
........\tenths.vhd
........\tenths.vho
........\tenths.xco
........\tenths_c_counter_binary_v8_0_xst_1.ngc
........\watchver.ise

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