Description: FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
File list (Check if you may need any files):
SDRAM Verilog代码及测试程序
...........................\CVS
...........................\...\Entries
...........................\...\Repository
...........................\...\Root
...........................\rtl
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\transcript
...........................\...\yadmc.v
...........................\...\yadmc_dpram.v
...........................\...\yadmc_sdram16.v
...........................\...\yadmc_spram.v
...........................\...\yadmc_sync.v
...........................\test
...........................\....\CVS
...........................\....\...\Entries
...........................\....\...\Repository
...........................\....\...\Root
...........................\....\mt48lc16m16a2.v
...........................\....\mt48lc16m16a2_modeltb.v
...........................\....\runsim.sh
...........................\....\transcript
...........................\....\yadmc_test.v
...........................\yadmc_block.dia
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