Description: A badic controller for the UART. It incorporates a
-- transmit and receive FIFO (from Max+Plus II s MegaWizard
-- plug-in manager). Note that no checking is done to see
-- whether the FIFOs are overflowing or not. This strictly
-- handles the transmitting and receiving of the data.
- [8counter_origin] - This is a design of 8bit binary counter
- [pgm] - uart vhdl code contains all the neceesar
File list (Check if you may need any files):
UART.txt
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