Description: VHDl written in a language with DPSK modulation and demodulation process, the program can be achieved relative phase modulation and demodulation. Can be run on xilinx ISE or QuartusII next.
- [DPSK] - DPSK modulation coding VHDL hardware imp
- [2DPSK] - VHDL language used to achieve digital tr
- [qpsk] - qpsk vhdl code ue to impelemented on fpg
- [dpsk] - DPSK describes the entire process, inclu
- [aksfskpsk] - Main completed the ask fsk psk modulatio
- [simulink_communication_system] - simulink to use on an instance of commun
- [cpu_four] - Verilog for FPGA-based quad-core schedul
- [MT29FxxG08xx] - MT of the NAND FLASH MT29FxxG08xx series
- [fsk] - VHDL hardware language using FSK modulat
- [qpsk] - qpsk modulation and demodulation of the
File list (Check if you may need any files):
cf_dpsk
.......\cf_dpsk.asm.rpt
.......\cf_dpsk.bdf
.......\cf_dpsk.done
.......\cf_dpsk.eda.rpt
.......\cf_dpsk.fit.rpt
.......\cf_dpsk.fit.smsg
.......\cf_dpsk.fit.summary
.......\cf_dpsk.flow.rpt
.......\cf_dpsk.map.rpt
.......\cf_dpsk.map.summary
.......\cf_dpsk.pin
.......\cf_dpsk.pof
.......\cf_dpsk.qpf
.......\cf_dpsk.qsf
.......\cf_dpsk.qws
.......\cf_dpsk.sim.rpt
.......\cf_dpsk.sof
.......\cf_dpsk.tan.rpt
.......\cf_dpsk.vwf
.......\db
.......\..\cf_dpsk.cbx.xml
.......\..\cf_dpsk.cmp.rdb
.......\..\cf_dpsk.dbp
.......\..\cf_dpsk.db_info
.......\..\cf_dpsk.eco.cdb
.......\..\cf_dpsk.eds_overflow
.......\..\cf_dpsk.fnsim.cdb
.......\..\cf_dpsk.fnsim.hdb
.......\..\cf_dpsk.fnsim.qmsg
.......\..\cf_dpsk.hier_info
.......\..\cf_dpsk.hif
.......\..\cf_dpsk.map.bpm
.......\..\cf_dpsk.map.cdb
.......\..\cf_dpsk.map.ecobp
.......\..\cf_dpsk.map.hdb
.......\..\cf_dpsk.map.logdb
.......\..\cf_dpsk.map.qmsg
.......\..\cf_dpsk.map_bb.cdb
.......\..\cf_dpsk.map_bb.hdb
.......\..\cf_dpsk.map_bb.logdb
.......\..\cf_dpsk.pre_map.cdb
.......\..\cf_dpsk.pre_map.hdb
.......\..\cf_dpsk.psp
.......\..\cf_dpsk.pss
.......\..\cf_dpsk.rtlv.hdb
.......\..\cf_dpsk.rtlv_sg.cdb
.......\..\cf_dpsk.rtlv_sg_swap.cdb
.......\..\cf_dpsk.sgdiff.cdb
.......\..\cf_dpsk.sgdiff.hdb
.......\..\cf_dpsk.sim.cvwf
.......\..\cf_dpsk.sim.hdb
.......\..\cf_dpsk.sim.qmsg
.......\..\cf_dpsk.sim.rdb
.......\..\cf_dpsk.simfam
.......\..\cf_dpsk.sld_design_entry.sci
.......\..\cf_dpsk.sld_design_entry_dsc.sci
.......\..\cf_dpsk.syn_hier_info
.......\..\cf_dpsk.tis_db_list.ddb
.......\..\mult_grn.tdf
.......\..\mult_qpo.tdf
.......\..\prev_cmp_cf_dpsk.map.qmsg
.......\..\prev_cmp_cf_dpsk.qmsg
.......\..\wed.wsf
.......\delay31.bsf
.......\delay31.vhd
.......\deley31.bsf
.......\div_10.bsf
.......\div_10.vhd
.......\low.bsf
.......\low.vhd
.......\lpm_mult0.bsf
.......\lpm_mult0.inc
.......\lpm_mult0.tdf
.......\lpm_mult0_waveforms.html
.......\pan.bsf
.......\pan.vhd
.......\pass.bsf
.......\pass.vhd
.......\simulation
.......\..........\modelsim
.......\..........\........\cf_dpsk.vho
.......\..........\........\cf_dpsk_modelsim.xrf
.......\..........\........\cf_dpsk_vhd.sdo
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