Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: cpld Download
 Description: CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
 Downloaders recently: [More information of uploader zhurencai]
 To Search: cpld vh
  • [fpga1394] - This is a control chip cpld 1394 Verilog
  • [scan_led] - An 8-bit digital tube scanner, after the
  • [i2c] - verilog
File list (Check if you may need any files):
cpld
....\ADD_VHDL
....\........\fadd_v.acf
....\........\fadd_v.hif
....\........\fadd_v.vhd
....\Count_VHDL
....\..........\count10_v.acf
....\..........\count10_v.fit
....\..........\count10_v.hif
....\..........\count10_v.jam
....\..........\count10_v.jbc
....\..........\count10_v.mmf
....\..........\count10_v.ndb
....\..........\count10_v.pin
....\..........\count10_v.pof
....\..........\count10_v.rpt
....\..........\count10_v.snf
....\..........\COUNT10_V.sym
....\..........\count10_v.vhd
....\..........\LIB.DLS
....\..........\U3524599.DLS
....\..........\U7551007.DLS
....\..........\U8766765.DLS
....\Divider_VHDL
....\............\divider_v.acf
....\............\divider_v.fit
....\............\divider_v.hif
....\............\divider_v.jam
....\............\divider_v.jbc
....\............\divider_v.mmf
....\............\divider_v.ndb
....\............\divider_v.pin
....\............\divider_v.pof
....\............\divider_v.rpt
....\............\divider_v.snf
....\............\DIVIDER_V.sym
....\............\divider_v.vhd
....\............\LIB.DLS
....\............\U0867274.DLS
....\............\U6527569.DLS
....\............\U8883682.DLS
....\D_Trig_VHDL
....\...........\dffe.acf
....\...........\dffe.hif
....\...........\dffe_v.acf
....\...........\dffe_v.fit
....\...........\dffe_v.hif
....\...........\dffe_v.jam
....\...........\dffe_v.jbc
....\...........\dffe_v.mmf
....\...........\dffe_v.ndb
....\...........\dffe_v.pin
....\...........\dffe_v.pof
....\...........\dffe_v.rpt
....\...........\dffe_v.snf
....\...........\DFFE_V.sym
....\...........\dffe_v.vhd
....\...........\LIB.DLS
....\...........\U6076995.DLS
....\...........\U8070528.DLS
....\...........\U8548312.DLS
....\keyinput
....\........\keyinput.acf
....\........\keyinput.fit
....\........\keyinput.hif
....\........\keyinput.jam
....\........\keyinput.jbc
....\........\keyinput.mmf
....\........\keyinput.ndb
....\........\keyinput.pin
....\........\keyinput.pof
....\........\keyinput.rpt
....\........\keyinput.scf
....\........\keyinput.snf
....\........\keyinput.tdf
....\........\keyinput.v
....\........\LIB.DLS
....\........\U3239746.DLS
....\........\U6275006.DLS
....\MUL_VHDL
....\........\LIB.DLS
....\........\mul.acf
....\........\mul.fit
....\........\mul.hif
....\........\mul.jam
....\........\mul.jbc
....\........\mul.mmf
....\........\mul.ndb
....\........\mul.pin
....\........\mul.pof
....\........\mul.rpt
....\........\mul.snf
....\........\MUL.sym
....\........\mul.vhd
....\........\U1576938.DLS
....\........\U3930065.DLS
....\........\U8649798.DLS
....\organ
....\.....\LIB.DLS
....\.....\organ.acf
    

CodeBus www.codebus.net