DDS_VHDL
........\220model.vhd
........\ADDER10B.bsf
........\ADDER10B.vhd
........\ADDER32B .vhd
........\altera_mf.vhd
........\cmp_state.ini
........\cyclone_atoms.vhd
........\cyclone_components.vhd
........\db
........\..\add_sub_1ph.tdf
........\..\add_sub_4rh.tdf
........\..\add_sub_5rh.tdf
........\..\add_sub_hsh.tdf
........\..\add_sub_r8i.tdf
........\..\altsyncram_2a71.tdf
........\..\altsyncram_3pj2.tdf
........\..\altsyncram_4vk2.tdf
........\..\altsyncram_9s51.tdf
........\..\altsyncram_a271.tdf
........\..\altsyncram_cpj2.tdf
........\..\altsyncram_g2c2.tdf
........\..\altsyncram_is51.tdf
........\..\altsyncram_m5u.tdf
........\..\altsyncram_s6l2.tdf
........\..\cntr_pd8.tdf
........\..\cntr_vv8.tdf
........\..\DDS_VHDL.asm.qmsg
........\..\DDS_VHDL.cbx.xml
........\..\DDS_VHDL.cmp.cdb
........\..\DDS_VHDL.cmp.hdb
........\..\DDS_VHDL.cmp.kpt
........\..\DDS_VHDL.cmp.logdb
........\..\DDS_VHDL.cmp.rdb
........\..\DDS_VHDL.cmp.tdb
........\..\DDS_VHDL.cmp0.ddb
........\..\DDS_VHDL.dbp
........\..\DDS_VHDL.db_info
........\..\DDS_VHDL.eco.cdb
........\..\DDS_VHDL.eda.qmsg
........\..\DDS_VHDL.fit.qmsg
........\..\DDS_VHDL.fnsim.hdb
........\..\DDS_VHDL.fnsim.qmsg
........\..\DDS_VHDL.hier_info
........\..\DDS_VHDL.hif
........\..\DDS_VHDL.map.cdb
........\..\DDS_VHDL.map.hdb
........\..\DDS_VHDL.map.logdb
........\..\DDS_VHDL.map.qmsg
........\..\DDS_VHDL.pre_map.cdb
........\..\DDS_VHDL.pre_map.hdb
........\..\DDS_VHDL.psp
........\..\DDS_VHDL.rtlv.hdb
........\..\DDS_VHDL.rtlv_sg.cdb
........\..\DDS_VHDL.rtlv_sg_swap.cdb
........\..\DDS_VHDL.sgdiff.cdb
........\..\DDS_VHDL.sgdiff.hdb
........\..\DDS_VHDL.signalprobe.cdb
........\..\DDS_VHDL.sld_design_entry.sci
........\..\DDS_VHDL.sld_design_entry_dsc.sci
........\..\DDS_VHDL.syn_hier_info
........\..\DDS_VHDL.tan.qmsg
........\..\decode_9ie.tdf
........\..\decode_ogi.tdf
........\..\mux_qfc.tdf
........\..\wed.zsf
........\DDS_VHD.cr.mti
........\DDS_VHDL.asm.rpt
........\DDS_VHDL.bsf
........\DDS_VHDL.cr.mti
........\DDS_VHDL.done
........\DDS_VHDL.dpf
........\DDS_VHDL.eda.rpt
........\DDS_VHDL.fit.eqn
........\DDS_VHDL.fit.rpt
........\DDS_VHDL.fit.smsg
........\DDS_VHDL.fit.summary
........\DDS_VHDL.flow.rpt
........\DDS_VHDL.map.eqn
........\DDS_VHDL.map.rpt
........\DDS_VHDL.map.summary
........\DDS_VHDL.pin
........\DDS_VHDL.pof
........\DDS_VHDL.qpf
........\DDS_VHDL.qsf
........\DDS_VHDL.qws
........\DDS_VHDL.sim.rpt
........\DDS_VHDL.sof
........\DDS_VHDL.tan.rpt
........\DDS_VHDL.tan.summary
........\DDS_VHDL.vhd
........\DDS_VHDL.vwf
........\DDS_VHDL_assignment_defaults.qdf
........\DDS_VHDL_nativelink_simulation.rpt
........\DDS_VHDL_TESTBENCH
........\..................\220model.vhd
........\..................\ADDER10B.vhd
........\..................\ADDER32B .vhd
........\..................\altera_mf.vhd
........\..................\altera_mf_components.vhd