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Title: fanzhen Download
 Description: Easy-to-use UART communication module, and the preparation of the adoption of Verilog simulation, directly available
 Downloaders recently: [More information of uploader qiangbing02]
 To Search:
  • [ata.tar] - The use of two types of Verilog and VHDL
  • [ATA_source_code] - ata controller Verilog source code, entr
File list (Check if you may need any files):
fanzhen
.......\clkdiv.v
.......\clkdiv.v.bak
.......\db
.......\..\myrs232.asm.qmsg
.......\..\myrs232.cbx.xml
.......\..\myrs232.cmp.bpm
.......\..\myrs232.cmp.cdb
.......\..\myrs232.cmp.ecobp
.......\..\myrs232.cmp.hdb
.......\..\myrs232.cmp.logdb
.......\..\myrs232.cmp.rdb
.......\..\myrs232.cmp.tdb
.......\..\myrs232.cmp0.ddb
.......\..\myrs232.cmp_bb.cdb
.......\..\myrs232.cmp_bb.hdb
.......\..\myrs232.cmp_bb.logdb
.......\..\myrs232.cmp_bb.rcf
.......\..\myrs232.dbp
.......\..\myrs232.db_info
.......\..\myrs232.eco.cdb
.......\..\myrs232.eda.qmsg
.......\..\myrs232.eds_overflow
.......\..\myrs232.fit.qmsg
.......\..\myrs232.fnsim.hdb
.......\..\myrs232.fnsim.qmsg
.......\..\myrs232.hier_info
.......\..\myrs232.hif
.......\..\myrs232.map.bpm
.......\..\myrs232.map.cdb
.......\..\myrs232.map.ecobp
.......\..\myrs232.map.hdb
.......\..\myrs232.map.logdb
.......\..\myrs232.map.qmsg
.......\..\myrs232.map_bb.cdb
.......\..\myrs232.map_bb.hdb
.......\..\myrs232.map_bb.logdb
.......\..\myrs232.pre_map.cdb
.......\..\myrs232.pre_map.hdb
.......\..\myrs232.psp
.......\..\myrs232.pss
.......\..\myrs232.rtlv.hdb
.......\..\myrs232.rtlv_sg.cdb
.......\..\myrs232.rtlv_sg_swap.cdb
.......\..\myrs232.sgdiff.cdb
.......\..\myrs232.sgdiff.hdb
.......\..\myrs232.signalprobe.cdb
.......\..\myrs232.sim.cvwf
.......\..\myrs232.sim.hdb
.......\..\myrs232.sim.qmsg
.......\..\myrs232.sim.rdb
.......\..\myrs232.sld_design_entry.sci
.......\..\myrs232.sld_design_entry_dsc.sci
.......\..\myrs232.syn_hier_info
.......\..\myrs232.tan.qmsg
.......\..\prev_cmp_myrs232.asm.qmsg
.......\..\prev_cmp_myrs232.eda.qmsg
.......\..\prev_cmp_myrs232.fit.qmsg
.......\..\prev_cmp_myrs232.map.qmsg
.......\..\prev_cmp_myrs232.sim.qmsg
.......\..\prev_cmp_myrs232.tan.qmsg
.......\..\wed.wsf
.......\myrs232.asm.rpt
.......\myrs232.cdf
.......\myrs232.done
.......\myrs232.dpf
.......\myrs232.eda.rpt
.......\myrs232.fit.rpt
.......\myrs232.fit.smsg
.......\myrs232.fit.summary
.......\myrs232.flow.rpt
.......\myrs232.map.rpt
.......\myrs232.map.smsg
.......\myrs232.map.summary
.......\myrs232.pin
.......\myrs232.pof
.......\myrs232.qpf
.......\myrs232.qsf
.......\myrs232.qws
.......\myrs232.sim.rpt
.......\myrs232.sof
.......\myrs232.tan.rpt
.......\myrs232.tan.summary
.......\myrs232.v
.......\myrs232.v.bak
.......\prev_cmp_myrs232.qmsg
.......\rec.v
.......\rec.v.bak
.......\send.v
.......\send.v.bak
.......\simulation
.......\..........\modelsim
.......\..........\........\myrs232.vo
.......\..........\........\myrs232_modelsim.xrf
.......\..........\........\myrs232_v.sdo
.......\..........\modelsim.ini
.......\..........\myrs232
.......\..........\.......\clkdiv
.......\..........\.......\......\verilog.psm
.......\..........\.......\......\_primary.dat
    

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