Description: Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
- [lzhu] - wrote it myself
- [Song_FPGA] - This is a source of FPGA can be achieved
- [liangzhu] - based max-plus2 development environment,
- [lctl_1.2] - Examples of CPLD procedures 1, EPM7128 c
- [HardwareflowerdesignEDAdesignreport] - Hardware electric circuit design EDA des
- [liangzhu] - Introduction to the Verilog HDL FPGA dev
- [dianzi] - Electric circuit design VHDL contains de
- [03_beep] - Through verilog language, passive buzzer
- [flower] - Flower contains VHDL are: top-level proc
- [hp3070prog] - Programming Xilinx XC9500 CPLDs on HP 30
File list (Check if you may need any files):
编程产生音乐.doc
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