Description: MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
File list (Check if you may need any files):
mux
...\db
...\..\mux.asm.qmsg
...\..\mux.cbx.xml
...\..\mux.cmp.ecobp
...\..\mux.cmp.rdb
...\..\mux.cmp0.ddb
...\..\mux.cmp_bb.cdb
...\..\mux.cmp_bb.hdb
...\..\mux.cmp_bb.logdb
...\..\mux.cmp_bb.rcf
...\..\mux.dbp
...\..\mux.db_info
...\..\mux.eco.cdb
...\..\mux.eds_overflow
...\..\mux.fit.qmsg
...\..\mux.fnsim.hdb
...\..\mux.fnsim.qmsg
...\..\mux.hier_info
...\..\mux.hif
...\..\mux.map.ecobp
...\..\mux.map.qmsg
...\..\mux.map_bb.logdb
...\..\mux.merge.qmsg
...\..\mux.pre_map.cdb
...\..\mux.pre_map.hdb
...\..\mux.psp
...\..\mux.pss
...\..\mux.rtlv.hdb
...\..\mux.rtlv_sg.cdb
...\..\mux.rtlv_sg_swap.cdb
...\..\mux.sgdiff.cdb
...\..\mux.sgdiff.hdb
...\..\mux.sim.hdb
...\..\mux.sim.qmsg
...\..\mux.sim.rdb
...\..\mux.sim_ori.vwf
...\..\mux.sld_design_entry.sci
...\..\mux.sld_design_entry_dsc.sci
...\..\mux.syn_hier_info
...\..\mux.tan.qmsg
...\..\mux_jcc.tdf
...\..\wed.wsf
...\mux.asm.rpt
...\mux.bdf
...\mux.bsf
...\mux.done
...\mux.dpf
...\mux.fit.rpt
...\mux.fit.smsg
...\mux.fit.summary
...\mux.flow.rpt
...\mux.map.rpt
...\mux.map.summary
...\mux.merge.rpt
...\mux.pin
...\mux.pof
...\mux.qpf
...\mux.qsf
...\mux.qws
...\mux.sim.rpt
...\mux.sof
...\mux.tan.rpt
...\mux.tan.summary
...\mux.v
...\mux.vwf
...\Pin_Setup.tcl
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