Description: With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- [select7] - VHDL seven people to vote for you for fr
- [compiler] - Tiny manually constructed language compi
- [vote7-2] - Seven people vote in the voting process
- [clock] - VHDL language before learning to do proc
- [Huffman] - huffman encoding and decoding the realiz
- [Verilog] - FPGA development, Verilog classic Guide,
- [seven] - This is my ISP programming in an indepen
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