Description: VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
- [LCDTV] - anticipates the source code, including t
- [ntsc_gen] - NTSC signal generator VHDL source code.
- [video] - Using VHDL video control procedures, inc
- [median] - Median filter of some algorithm, and the
- [shipin] - Digital video acquisition and processing
- [video_process_base_on_DSPandFPGA] - Based on high-speed digital signal proce
- [Ucos_IIchese] - Chinese Annotation Ucos_II2.52 source Au
- [720X576] - Using Verilog hardware description langu
- [video-scaler] - video scalar for solmon decoding
- [resolutionquartusII] - Written resolution with the verilog sour
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