Description: SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct.
- [shanghai-arm] - Shanghai Jiaotong University of embedded
- [fifo] - The use of Verilog language, the FPGA co
- [RS232] - Realize this experiment, PS/2 interface
- [RS232uart(VHDL)] - Depth of 256-byte Serial RS232 procedure
- [Two_Port_RAM_lab] - 通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示
- [P89V51RD] - Schematic 89c51usb emulator, super rod,
- [WebContent] - Test system software features related to
- [DP_RAM_lab] - SmartGen generated using a 2k* 8 Dual Po
File list (Check if you may need any files):
Flash_ROM_lab
.............\ctrl_ROM.v
.............\flashROM_DATA.txt
.............\RDROM_top.v
.............\send.v
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