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Title: I2C Download
 Description: IIC communications protocol IP core
 Downloaders recently: [More information of uploader shigx2007]
  • [iic] - IIC bus standard Verilog source code i2c
  • [i2c] - Based on the VHDL language to achieve th
  • [NiosII] - Through the study of automobile anti-the
  • [i2c] - VHDL language I2C core, has already been
  • [i2c] - I2C procedures, has already been verifie
  • [can] - Based on Verilog HDL a CAN bus IP core.
  • [I2C] - I2C interface FPGA to achieve
  • [i2c_master_slave_core] - I2C master/slave IP core
  • [i2c] - This is an IIC interface procedures for
  • [IIC] - fpga implementation of serial communicat
File list (Check if you may need any files):
I2C
...\automake.log
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.ise
...\I2C.ise_ISE_Backup
...\I2C_ise6_bak.zip
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl.v.bak
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl.v.bak
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_defines.v.bak
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top.v.bak
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\wb_master_model.v.bak
...\work
...\....\glbl
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\i2c_slave_model
...\....\...............\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\_info
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg07
...\...\....\.....\i2c_master_bit_ctrl.bin
...\...\....\vlg5C
...\...\....\.....\i2c_master_byte_ctrl.bin
...\...\....\vlg67
...\...\....\.....\i2c_master_top.bin
...\__projnav
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log
    

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