Description: MCU and FPGA co-component systems, FPGA data acquisition, single-chip microcomputer for data processing. Board are a company. Attached flow, and describe in detail.
- []FPGAPDF] - FPGA design instruction manual PDF versi
- [Altera-FPGA-Guide] - Altera FPGA development tools detailed g
- [IO] - C51-CPLD joint development board schemat
- [LCD] - AVR ATmega128L the LCD process
- [AD5320_c] - err
- [yixiang] - Sinusoidal phase-shifting network, enter
- [sourse] - NC-based single-chip switching power sup
- [www] - The paper has designed a low frequency d
- [FPGAfir] - FPGA realization of FIR decimation filte
- [key-dejitter] - Key de-jittering module to avoid system
File list (Check if you may need any files):
PROJECT
.......\TEST.C
.......\test3
.......\.....\BZH.bsf
.......\.....\BZH.vhd
.......\.....\cdfs.bsf
.......\.....\cdfs.cmp
.......\.....\cdfs.vhd
.......\.....\db
.......\.....\..\add_sub_0fc.tdf
.......\.....\..\add_sub_1fc.tdf
.......\.....\..\add_sub_2fc.tdf
.......\.....\..\add_sub_3dc.tdf
.......\.....\..\add_sub_3fc.tdf
.......\.....\..\add_sub_4dc.tdf
.......\.....\..\add_sub_4fc.tdf
.......\.....\..\add_sub_5dc.tdf
.......\.....\..\add_sub_5fc.tdf
.......\.....\..\add_sub_6dc.tdf
.......\.....\..\add_sub_6fc.tdf
.......\.....\..\add_sub_7dc.tdf
.......\.....\..\add_sub_7fc.tdf
.......\.....\..\add_sub_8dc.tdf
.......\.....\..\add_sub_8fc.tdf
.......\.....\..\add_sub_9dc.tdf
.......\.....\..\add_sub_9fc.tdf
.......\.....\..\add_sub_adc.tdf
.......\.....\..\add_sub_afc.tdf
.......\.....\..\add_sub_bdc.tdf
.......\.....\..\add_sub_i4h.tdf
.......\.....\..\add_sub_jec.tdf
.......\.....\..\add_sub_kec.tdf
.......\.....\..\add_sub_lec.tdf
.......\.....\..\add_sub_mac.tdf
.......\.....\..\add_sub_mec.tdf
.......\.....\..\add_sub_n4h.tdf
.......\.....\..\add_sub_nec.tdf
.......\.....\..\add_sub_oec.tdf
.......\.....\..\add_sub_pec.tdf
.......\.....\..\add_sub_q4h.tdf
.......\.....\..\add_sub_qec.tdf
.......\.....\..\add_sub_rec.tdf
.......\.....\..\add_sub_sec.tdf
.......\.....\..\add_sub_tec.tdf
.......\.....\..\add_sub_uec.tdf
.......\.....\..\add_sub_vec.tdf
.......\.....\..\alt_u_div_cue.tdf
.......\.....\..\alt_u_div_due.tdf
.......\.....\..\alt_u_div_eue.tdf
.......\.....\..\alt_u_div_fue.tdf
.......\.....\..\alt_u_div_gue.tdf
.......\.....\..\alt_u_div_hue.tdf
.......\.....\..\alt_u_div_iue.tdf
.......\.....\..\DEVIDE64.cbx.xml
.......\.....\..\DEVIDE64.cmp.rdb
.......\.....\..\DEVIDE64.db_info
.......\.....\..\DEVIDE64.eco.cdb
.......\.....\..\DEVIDE64.hif
.......\.....\..\DEVIDE64.map.qmsg
.......\.....\..\DEVIDE64.sld_design_entry.sci
.......\.....\..\lpm_divide_1np.tdf
.......\.....\..\lpm_divide_2np.tdf
.......\.....\..\lpm_divide_3np.tdf
.......\.....\..\lpm_divide_4np.tdf
.......\.....\..\lpm_divide_cpp.tdf
.......\.....\..\lpm_divide_jcr.tdf
.......\.....\..\lpm_divide_kcr.tdf
.......\.....\..\sign_div_unsign_enh.tdf
.......\.....\..\sign_div_unsign_fnh.tdf
.......\.....\..\sign_div_unsign_gnh.tdf
.......\.....\..\sign_div_unsign_hnh.tdf
.......\.....\..\sign_div_unsign_inh.tdf
.......\.....\..\sign_div_unsign_jnh.tdf
.......\.....\..\sign_div_unsign_knh.tdf
.......\.....\..\test3.asm.qmsg
.......\.....\..\test3.cbx.xml
.......\.....\..\test3.cmp.cdb
.......\.....\..\test3.cmp.hdb
.......\.....\..\test3.cmp.kpt
.......\.....\..\test3.cmp.logdb
.......\.....\..\test3.cmp.rdb
.......\.....\..\test3.cmp.tdb
.......\.....\..\test3.cmp0.ddb
.......\.....\..\test3.dbp
.......\.....\..\test3.db_info
.......\.....\..\test3.eco.cdb
.......\.....\..\test3.eds_overflow
.......\.....\..\test3.fit.qmsg
.......\.....\..\test3.hier_info
.......\.....\..\test3.hif
.......\.....\..\test3.map.cdb
.......\.....\..\test3.map.hdb
.......\.....\..\test3.map.logdb
.......\.....\..\test3.map.qmsg
.......\.....\..\test3.pre_map.cdb
.......\.....\..\test3.pre_map.hdb
.......\.....\..\test3.psp
.......\.....\..\test3.pss
.......\.....\..\test3.rtlv.hdb
.......\.....\..\test3.rtlv_sg.cdb
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