Description: Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data, send data back data+1
- [uart_verilog] - include UART port of VERILOG source, the
- [ uart from opencores] - VHDL implement serial port, it can commu
- [FTCJTAG] - FTDI FIFO JTAG programming paradigm
- [serial] - VerilogHDL routine, and realize the basi
- [uart] - Single-chip serial communication princip
- [uart] - MAXII based on the RS232 serial communic
- [15Altera_IP] - Which contains 15 nuclear altera the IP
- [mini-uart] - Verilog implementation mini-uart, code F
- [uart8] - Libero provided the use of asynchronous
- [uart] - uart verilog
File list (Check if you may need any files):
UART
....\designer
....\........\impl1
....\........\.....\designer.log
....\........\.....\uart_test.adb
....\........\.....\uart_test.dtf
....\........\.....\.............\verify.log
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\hdl
....\...\rec.v
....\...\send.v
....\...\uart_test.v
....\simulation
....\..........\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\synthesis
....\.........\.recordref
....\.........\stdout.log
....\.........\syntmp
....\.........\......\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\UART.prj
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