Description: This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open.
- [examples of VHDL program] - these are typical program of VHDL.there
- [Verilog-HDL] - the CD-ROM include Verilog-HDL Practice
- [CpldandEepromI2c] - verilog I2c agreement prepared by the pr
- [RS232] - RS232 protocol specification, on a clear
- [led] - 10脦 禄8 露 脦LED渭脛脡 篓 脙猫脧脭脢 戮 鲁 脤脨貌 拢 卢 驴 脡
- [EEPROMpresentation] - DIP switch for the use of programmable d
- [CPLD_Design_50] - 50 cases of practical CPLD design, very
- [VerilogHDL] - Explain the very good Verilog HDL teachi
- [rs232] - This is cpld, EPM240 data communication
- [H6502] - The standard H.264 decoder all verilog s
File list (Check if you may need any files):
db
..\RoyCPLD.asm.qmsg
..\RoyCPLD.asm_labs.ddb
..\RoyCPLD.cbx.xml
..\RoyCPLD.cmp.cdb
..\RoyCPLD.cmp.hdb
..\RoyCPLD.cmp.logdb
..\RoyCPLD.cmp.rdb
..\RoyCPLD.cmp.tdb
..\RoyCPLD.cmp0.ddb
..\RoyCPLD.dbp
..\RoyCPLD.db_info
..\RoyCPLD.eco.cdb
..\RoyCPLD.fit.qmsg
..\RoyCPLD.hier_info
..\RoyCPLD.hif
..\RoyCPLD.map.cdb
..\RoyCPLD.map.hdb
..\RoyCPLD.map.logdb
..\RoyCPLD.map.qmsg
..\RoyCPLD.pre_map.cdb
..\RoyCPLD.pre_map.hdb
..\RoyCPLD.psp
..\RoyCPLD.pss
..\RoyCPLD.rpp.qmsg
..\RoyCPLD.rtlv.hdb
..\RoyCPLD.rtlv_sg.cdb
..\RoyCPLD.rtlv_sg_swap.cdb
..\RoyCPLD.sgate.rvd
..\RoyCPLD.sgate_sm.rvd
..\RoyCPLD.sgdiff.cdb
..\RoyCPLD.sgdiff.hdb
..\RoyCPLD.signalprobe.cdb
..\RoyCPLD.sld_design_entry.sci
..\RoyCPLD.sld_design_entry_dsc.sci
..\RoyCPLD.syn_hier_info
..\RoyCPLD.tan.qmsg
key.v
led.v
RoyCPLD.asm.rpt
RoyCPLD.cdf
RoyCPLD.done
RoyCPLD.dpf
RoyCPLD.fit.rpt
RoyCPLD.fit.smsg
RoyCPLD.fit.summary
RoyCPLD.flow.rpt
RoyCPLD.map.rpt
RoyCPLD.map.smsg
RoyCPLD.map.summary
RoyCPLD.pin
RoyCPLD.pof
RoyCPLD.qpf
RoyCPLD.qsf
RoyCPLD.qws
RoyCPLD.tan.rpt
RoyCPLD.tan.summary
RoyCPLD.v
rs232_rec_fun.v
rs232_send_fun.v
rs232_speed.v
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