Description: 4 electronic smart locks, based on the VHDL design language, MAX+ PLUS Ⅱ environment to achieve
- [PLW] - electronic locks VHDL programming, I won
- [VHDL] - Southeast University, Electrical and Ele
- [4bit.elock] - 4 electronic code locks, has detailed th
- [password_lock] - Electronic code locks, FPGA-based design
- [sopcast] - Unlock the completion of overtime alarm,
- [ElectronicCodeLock] - The design of a universal electronic cod
- [key] - Password lock controller Designed a pass
File list (Check if you may need any files):
EDA课程设计做的用VHDL写的智能电子密码锁
.......................................\EDA_LOCK_ALL
.......................................\............\EDA_LOCK_ALL
.......................................\............\............\4SUOCUNQI_K
.......................................\............\............\...........\db
.......................................\............\............\...........\..\suocunqi4.asm.qmsg
.......................................\............\............\...........\..\suocunqi4.cbx.xml
.......................................\............\............\...........\..\suocunqi4.cmp.cdb
.......................................\............\............\...........\..\suocunqi4.cmp.hdb
.......................................\............\............\...........\..\suocunqi4.cmp.logdb
.......................................\............\............\...........\..\suocunqi4.cmp.rdb
.......................................\............\............\...........\..\suocunqi4.cmp.tdb
.......................................\............\............\...........\..\suocunqi4.cmp0.ddb
.......................................\............\............\...........\..\suocunqi4.dbp
.......................................\............\............\...........\..\suocunqi4.db_info
.......................................\............\............\...........\..\suocunqi4.eco.cdb
.......................................\............\............\...........\..\suocunqi4.eds_overflow
.......................................\............\............\...........\..\suocunqi4.fit.qmsg
.......................................\............\............\...........\..\suocunqi4.hier_info
.......................................\............\............\...........\..\suocunqi4.hif
.......................................\............\............\...........\..\suocunqi4.map.cdb
.......................................\............\............\...........\..\suocunqi4.map.hdb
.......................................\............\............\...........\..\suocunqi4.map.logdb
.......................................\............\............\...........\..\suocunqi4.map.qmsg
.......................................\............\............\...........\..\suocunqi4.pre_map.cdb
.......................................\............\............\...........\..\suocunqi4.pre_map.hdb
.......................................\............\............\...........\..\suocunqi4.psp
.......................................\............\............\...........\..\suocunqi4.pss
.......................................\............\............\...........\..\suocunqi4.rtlv.hdb
.......................................\............\............\...........\..\suocunqi4.rtlv_sg.cdb
.......................................\............\............\...........\..\suocunqi4.rtlv_sg_swap.cdb
.......................................\............\............\...........\..\suocunqi4.sgdiff.cdb
.......................................\............\............\...........\..\suocunqi4.sgdiff.hdb
.......................................\............\............\...........\..\suocunqi4.sim.cvwf
.......................................\............\............\...........\..\suocunqi4.sim.hdb
.......................................\............\............\...........\..\suocunqi4.sim.qmsg
.......................................\............\............\...........\..\suocunqi4.sim.rdb
.......................................\............\............\...........\..\suocunqi4.sld_design_entry.sci
.......................................\............\............\...........\..\suocunqi4.sld_design_entry_dsc.sci
.......................................\............\............\...........\..\suocunqi4.syn_hier_info
.......................................\............\............\...........\..\suocunqi4.tan.qmsg
.......................................\............\............\...........\..\wed.wsf
.......................................\............\......
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