ref-ddr-sdram-verilog sdram verilog source code re

Title: ref-ddr-sdram-verilog

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Embeded-SCM Develop
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File Size:
883kb
Update:
2012-11-26
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Uploaded by:
skyblue51

Description: sdram verilog source code realizes

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To Search: verilog sdram sdram verilog ddr DDR SDRAM ddr verilog verilog sdram verilog ram Verilog DDRam SDRAM code in VHDL

[standardSDRSDRAMcontrollerreferencedesign_v] - standard SDR SDRAM controller reference
[sdram] - SDRAM controller here consider SDRAM con
[xapp195] - signed_mult multiplier is used DSP desig
[very-good-ok-ref-ddr-sdram-verilog] - Sdr SDRAM controller reference design, v
[SystemOfTaxiFeeBasedOnVerilogHDL] - Abstract: Shanghai taxi meter as an exam
[mx27ads_x33] - i.MX27 development board schematic detai
[verilog] - A group of exercises, on a number of VHD

File list (Check if you may need any files):

doc
...\ddr_sdram.pdf
model
.....\mt46v4m16.v
readme.txt
route
.....\ddr_sdram.csf
.....\ddr_sdram.esf
.....\ddr_sdram.psf
.....\ddr_sdram.quartus
.....\ddr_sdram.vqm
.....\pll1.v
simulation
..........\ddr_compile_all.v
..........\ddr_sdram_tb.v
..........\modelsim.ini
..........\readme.txt
..........\work
..........\....\altclklock
..........\....\..........\verilog.psm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\ddr_command
..........\....\...........\verilog.psm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\ddr_control_interface
..........\....\.....................\verilog.psm
..........\....\.....................\_primary.dat
..........\....\.....................\_primary.vhd
..........\....\ddr_data_path
..........\....\.............\verilog.psm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\ddr_sdram
..........\....\.........\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\ddr_sdram_tb
..........\....\............\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\mt46v4m16
..........\....\.........\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\pll1
..........\....\....\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\_info
source
......\altclklock.v
......\ddr_Command.v
......\ddr_control_interface.v
......\ddr_data_path.v
......\ddr_sdram.v
......\Params.v
......\pll1.v
synthesis
.........\synplicity
.........\..........\ddr_data_path.srm
.........\..........\ddr_data_path.srr
.........\..........\ddr_data_path.srs
.........\..........\ddr_data_path.tlg
.........\..........\ddr_data_path.xrf
.........\..........\ddr_sdram.prj
.........\..........\ddr_sdram.sdc
.........\..........\ddr_sdram.srm
.........\..........\ddr_sdram.srr
.........\..........\ddr_sdram.srs
.........\..........\ddr_sdram.tcl
.........\..........\ddr_sdram.tlg
.........\..........\ddr_sdram.vqm
.........\..........\ddr_sdram.xrf
.........\..........\ddr_sdram_cons.tcl
.........\..........\ddr_sdram_rm.tcl

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