Description: Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.
- [8LED_Test] - Eight digital tube experiments S3C44B0 E
- [LCD_Test] - Directory file structure: for s3c44b0lcd
- [Circle0805] - A circular instrument control, you can s
- [Wormhole_Simulation_Code] - This code was used to produce simulation
- [usb_phy] - usb interface protocol. It was tested wi
- [amba3core] - amba3 sva fully validate the code, and t
- [fpga] - fpga+ sdram+ PHY chip design schematic
- [asymmetric_fifo] - Asymmetric high-speed synchronous FIFO,
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