Description: the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
- [primetime] - This is the VHDL language delay the test
- [WebServer(VC6.0).Rar] - the procedures can provide functional We
- [uart] - This is the UART controller, has been ru
- [delay] - VHDL state machine used to achieve preci
- [LCD] - LCD1602 process, just simply show the co
- [vhdlyanshi] - With regard to the delay in vhdl languag
- [yanshi] - VHDL delay to the start of the function
File list (Check if you may need any files):
Download