weifenqi Differentiator: the use of digital phase- - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Title: weifenqi

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
123.66kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
river02

Description: Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules

Downloaders recently: [More information of uploader river02]

To Search: vhdl weifenqi

[pll_improvement] - an improved DPLL design an improved desi
[verilogpll1234] - verilog DPLL the design, verilog based o
[digital_loopback] - ti-based company 6713dsp the DPLL, the o
[FPGA_bit_clock_data_recovery] - New FPGA-based data bit sync clock extra
[333] - For bit synchronization, a basis functio
[tongbujishudexiangguanziliao] - Relevant information of Synchronous tech
[bit_synch] - I wrote the MSK demodulation synchroniza
[Matlab] - Matlab source code, including the interp
[tutorial_4] - simple fpga basic design using VHDL code

File list (Check if you may need any files):

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.