Description: Arbitrary frequency of VHDL realize that if the needs of specific parameters, simply change the process parameters of the sub-band can be realized.
- [fenpin] - Arbitrary number of sub-frequency of the
- [DDS_vhdl] - The realization of arbitrary fractional-
- [de_PL_MPSK] - Based on the VHDL hardware description l
- [hdb3] - Realize HDB3 communication in the proces
- [UART] - Input clock 20M, the baud rate for 9600,
- [080513154000] - Parallel to serial VHDL description: Bas
- [UART] - Using FPGA to achieve the RS232 asynchro
- [huaweixiaoshufenpin] - Huawei s patented fractional-N contents
- [Frequency_divider] - With VERILOG HDL realize arbitrary frequ
- [divclk] - Practical arbitrary clock frequency Veri
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