SD card controller can just read data using 1 bit SD mode. I have written this core for nios 2 CPU, Cyclone, but I think it can works With other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and The CPU clock is 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck - SD card controller can just read the data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. The Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the thewire 1:5). If you have a wish you can on your this core. Good luck

sd卡读写IP
..........\sd
..........\..\class.ptf
..........\..\crc_unit_16.v
..........\..\crc_unit_7.v
..........\..\inc
..........\..\...\altera_avalon_camelot_sd_controller_regs.h
..........\..\mk_user_logic_Camelot_SD_Controller.pl
..........\..\readme.txt
..........\..\sd.v
..........\..\sd_controller.v
..........\..\sd_host.v
..........\..\soft example for nios2
..........\..\......................\main.cpp

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．